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| w6691 preliminary isdn s/t interface transceiver publication release date: sep 2001 1 revision 1.1 w6691 isdn s/t interface transceiver data sheet the information described in this document is the exclusive intellectual property of winbond electronics corp and shall not be reproduced without permission from winbond. winbond is providing this document only for reference purposes for w6691-based system design. winbond assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice.
preliminary w6691 publication release date: sep 2001 2 revision 1.1 table of contents revision history............................................................................................................... ............... 7 1. general description......................................................................................................... ........ 8 2. features.................................................................................................................... ..................... 9 3. pin configurations .......................................................................................................... ........ 10 4. pin description ............................................................................................................. ............. 13 5. system diagram and applications..................................................................................... 16 6. block diagram ............................................................................................................... ............ 18 7. functional descriptions..................................................................................................... .. 19 7.1.1 main block functions ..................................................................................................... .................19 7.1.2 interface and operating modes ............................................................................................ ...........20 7.2.1 s/t interface transmitter/receiver....................................................................................... ...........20 7.2.2 receiver clock recovery and timing generation ..........................................................................25 7.2.3 layer 1 activation/deactivation .......................................................................................... .............26 7.2.4 layer 1 activation /deactivation in lt-s mode............................................................................ ....32 7.2.5 d channel access control ................................................................................................. .............35 7.2.6 frame alignment .......................................................................................................... ...................36 7.2.7multiframe synchronization ................................................................................................ ..............38 7.2.8test functions ............................................................................................................ ......................40 7.3 b channel switching ........................................................................................................ ................ 41 7.4 pcm port ................................................................................................................... ....................... 42 7.5 d channel hdlc controller .................................................................................................. ........... 42 7.5.1 d channel message transfer modes ......................................................................................... .....44 7.5.2 reception of frames in d channel ......................................................................................... ........45 7.5.3 transmission of frames in d channel ...................................................................................... ......46 7.6 gci mode serial interface bus .............................................................................................. ........... 47 7.6.1 gci mode c/i channel handling ............................................................................................ .........49 7.6.2 gci mode monitor channel handling........................................................................................ ......50 7.7 8-bit microprocessor interface ............................................................................................ ............ 52 8 register desrcriptions....................................................................................................... ... 53 8.1 d channel hdlc controller register address map......................................................................... 53 8.2 gci bus control register address map ....................................................................................... .... 54 8.3 miscellaneous register address map ......................................................................................... ..... 55 8.4 d channel hdlc controller register memory map ......................................................................... 55 preliminary w6691 publication release date: sep 2001 3 revision 1.1 8.5 gci bus register memory map................................................................................................ ........ 57 8.6 miscellaneous register memory map .......................................................................................... .... 58 table 8.6 miscellaneous register memory map .................................................................................... 58 8.7 d channel hdlc controller register description............................................................................. 58 8.7.1 d_ch receive fifo d_rfifo read address 00h......................................................................58 8.7.2 d_ch transmit fifo d_xfifo write address 01h.....................................................................59 8.7.3 d_ch command register d_cmdr write address 02h .............................................................59 8.7.4 d_ch mode register d_mode read/write address 03h ..........................................................60 8.7.5 interrupt status register ista read_clear address 04h.......................................................61 8.7.6 interrupt mask register imask read/write address 05h...........................................................63 8.7.7 d_ch extended interrupt register d_exir read_clear address 06h .......................................63 8.7.8 d_ch extended interrupt mask register d_exim read/write address 07 h ...............................64 8.7.9 d_ch transmitter status register d_xsta read address 0ah..............................................65 8.7.10 d_ch receive status register d_rsta read address 0bh ................................................65 8.7.11 d_ch sapi address mask d_sam read/write address 0eh ................................................66 8.7.12 d_ch sapi1 register d_sap1 read/write address 0fh........................................................67 8.7.13 d_ch sapi2 register d_sap2 read/write address 10h ........................................................67 8.7.14 d_ch tei address mask d_tam read/write address 11h ....................................................67 8.7.15 d_ch tei1 register d_tei1 read/write address 12h..........................................................68 8.7.16 d_ch tei2 register d_tei2 read/write address 13h..........................................................68 8.7.17 d_ch receive frame byte count high d_rbch read address 16h .....................................69 8.7.18 d_ch receive frame byte count low d_rbcl read address 17h....................................69 8.8 gci bus register description............................................................................................... ............ 70 8.8.1 channel selection register csel read/write address 18h ................................................70 8.8.2 command/indication receive register cir read address 1ah...............................................70 8.8.3 command/indication transmit register cix read/write address 1bh ...................................71 8.8.4 s/q channel receive register sqr read address 1ch ...........................................................71 8.8.5 s/q channel transmit register sqx read/write address 1dh ...............................................72 8.8.6 monitor receive channel 0 mo0r read address 20h..........................................................72 8.8.7 monitor transmit channel 0 mo0x read/write address 21h................................................72 8.8.8 monitor channel 0 interrupt register mo0i read_clear address 22h .................................73 8.8.9 monitor channel 0 control register mo0c read/write address 23h .....................................73 8.8.10 gci mode control/status register gcr read address 26h .....................................74 8.8.11 monitor receive channel 1 register mo1r read address 27h ...........................................75 8.8.12 monitor transmit channel 1 register mo1x read/write address 28h.......................75 8.8.13 monitor channel 1 interrupt register mo1i read_clear address 29h ...............................76 8.8.14 monitor channel 1 control register mo1c read/write address 2ah ....................................76 8.8.14 gci ci1 indication register ci1r read address 31h ........................................................77 preliminary w6691 publication release date: sep 2001 4 revision 1.1 8.8.16 gci ci1 command register ci1x read/write address 32h................................................77 8.8.17 gci extended interrupt register gci_exir read_clear address 34h.....................................78 8.8.18 gci extended interrupt mask register gci_exim read/write address 35h .........................78 8.9 miscellaneous register ..................................................................................................... ............... 79 8.9.1 timer 1 register timr1 read/write address 38h ....................................................................79 8.9.2 timer 2 timr2 read/ write address 39h................................................................80 8.9.3 peripheral control register pcr read/write address 3ah........................................................81 8.9.4 peripheral i/o data register piodr read/write address 3bh ............................................82 8.9.5 sfctl switch functional control register read/write address 3ch 83 8.9.6 actl1 auxiliary control register 1 read/write address 3dh ..................................................84 8.9.7 actl2 auxiliary control register2 read/write address 3eh ..................................................85 8.9.8 actl3 auxiliary control register 3 read/write address 3fh .................................................86 8.10 b1 channel hdlc controller register address map .................................................................... 86 8.11 b1 channel hdlc controller register memory map ...................................................................... 87 8.11.1 b1_ch receive fifo b1_rfifo read address 50h ..........................................................87 8.11.2 b1_ch transmit fifo b1_xfifo write address 51h ...........................................................87 8.11.3 b1_ch command register b1_cmdr read/write address 53h ................................................88 8.11.4 b1_ch mode register b1_mode read/write address 54h....................................................89 8.11.5 b1_ch extended interrupt register b1_exir read_clear address 56h...................................90 8.11.6 b1_ch extended interrupt mask register b1_exim read/write address 57h ................91 8.11.7 b1_ch status register b1_star read address 58h.......................................................91 8.11.8 b1_ch address mask register 1 b1_adm1 read/write address 59h ..................................92 8.11.9 b1_ch address mask register 2 b1_adm2 read/write address 5ah .....................................93 8.11.10 b1_ch address register 1 b1_adr1 read/write address 5bh ...........................................93 8.11.11 b1_ch address register 2 b1_adr2 read/write address 5ch ...........................................93 8.11.12 b1_ch receive frame byte count low b1_rbcl read address 5dh ................................93 8.11.13 b1_ch receive frame byte count high b1_rbch read address 5eh ...............................94 8.11.14b1_ch transmit idle pattern b1_idle read/write address 5fh .............................................94 8.12 b2 channel hdlc controller register address map ..................................................................... 95 8.13 b2 channel hdlc controller register memory map ..................................................................... 95 9. electrical characteristics ................................................................................................ 97 9.1 absolute maximum rating.................................................................................................... ............ 97 9.2 power supply ............................................................................................................... .................... 97 9.3 dc characteristics......................................................................................................... ................... 97 9.4 preliminary switching characteristics ...................................................................................... ........ 99 9.4.1 pcm interface timing ..................................................................................................... .................99 9.4.2 8-bit microprocessor timing .............................................................................................. ............101 preliminary w6691 publication release date: sep 2001 5 revision 1.1 9.5 ac timing test conditions.................................................................................................. ........... 104 10. ordering information ....................................................................................................... . 104 11. package dimensions ......................................................................................................... ... 105 list of figures fig.3.1 w6691 pin configuration - intel bus mode ............................................................. 10 fig.3.2 w6691 pin configuration ? motorola bus mode .................................................. 12 fig.5.1 isdn internet passive s-card with two pots connections ........................... 16 fig.5.2 isdn paxb application .................................................................................................. ... 17 fig.6.1 w6691 functional block diagram .............................................................................. 18 fig.7.1 frame structure at s/t interface ........................................................................... 21 fig.7.2 w6691 wiring configuration in te applications.................................................. 22 fig.7.3 external transmitter circuitry .............................................................................. 23 fig.7.4 external receiver circuitry...................................................................................... 24 fig.7.5 layer 1 activation/deaction state diagram ? normal mode .......................... 30 fig.7.6 layer 1 activation/deactivation state diagram - special mode ................... 31 fig.7.7 layer 1 activation/deactivation state diagram in lt-s.................................... 34 fig.7.9 ssp and scp test signals .............................................................................................. 4 1 fig.7.10 gci te mode channel structure.............................................................................. 48 fig.7.11 gci non ?terminal mode channel structure..................................................... 49 list of tables table 7.1 output phase delay compensation table ........................................................ 25 table 7.2 layer 1 command codes ........................................................................................... 28 table 7.3 layer 1 indication codes ......................................................................................... 28 table 7.4 layer 1 command codes ........................................................................................... 33 table 7.5 layer 1 indication codes ......................................................................................... 33 table 7.8 d priority classes ................................................................................................... .. 35 table 7.9 d priority commands/indications ........................................................................ 35 table 7.10 multiframe structure in s/t interface .......................................................... 39 table 8.1 d channel hdlc controller register address map.................................... 53 table 8.2 gci bus control register address map ........................................................... 54 table 8.3 miscellaneous register address map .............................................................. 55 table 8.4 d channel hdlc controller register memory map..................................... 55 preliminary w6691 publication release date: sep 2001 6 revision 1.1 table 8.5 gci bus register memory map ............................................................................... 57 table 8.7 b1 channel hdlc controller register address map.................................. 86 table 8.8 b1 channel hdlc controller register memory map ................................... 87 table 8.9 b2 channel hdlc controller register address map.................................. 95 table 8.10 b2 channel hdlc controller register memory map ................................. 95 list of tables table 7.1 output phase delay compensation table ........................................................ 25 table 7.2 layer 1 command codes ........................................................................................... 28 table 7.3 layer 1 indication codes ......................................................................................... 28 table 7.4 layer 1 command codes ........................................................................................... 33 table 7.5 layer 1 indication codes ......................................................................................... 33 table 7.8 d priority classes ................................................................................................... .. 35 table 7.9 d priority commands/indications ........................................................................ 35 table 7.10 multiframe structure in s/t interface .......................................................... 39 table 8.1 d channel hdlc controller register address map.................................... 53 table 8.2 gci bus control register address map ........................................................... 54 table 8.3 miscellaneous register address map .............................................................. 55 table 8.4 d channel hdlc controller register memory map..................................... 55 table 8.5 gci bus register memory map ............................................................................... 57 table 8.7 b1 channel hdlc controller register address map.................................. 86 table 8.8 b1 channel hdlc controller register memory map ................................... 87 table 8.9 b2 channel hdlc controller register address map.................................. 95 table 8.10 b2 channel hdlc controller register memory map ................................. 95 preliminary w6691 publication release date: sep 2001 7 revision 1.1 revision history date version content of revision jan 2001 1.0 the first version is edited. sep 2001 1.1 1. w6691 pin configuration -- intel bus mode is modified on page11. 2. w6691 pin configuration ? motorola bus mode is modified on page 12 3. pin description is modified on page 13. 4. the chapter 7.1.2 interface and operating mode description is changed on page 20. 5. the transformer ratio 1:1 is changed to 2:1 on fig 7.3 and 7.4 page 23 and page 24. preliminary w6691 publication release date: sep 2001 8 revision 1.1 1. general description w6691 consists of one d channel hdlc controller and two b hdlc controller channel access. the hdlc controller facilitates efficient access to signaling, data and voice services. it provides multiplex/non- mutiplexe 8- bit microprocessor interface. the interface is selected by external mbs selection. in addition, w6691 can be operated in te, lt-s and lt-t mode programmed by external pin. in te mode, w6691 provides pcm bus or gci bus to connect with codec. in lt mode, it can used in nt2 application. w6691 also provides various b channel switching function among pcm, gci and layer2. it adopts 3.3v process to manufacture. the fifo size of d channel is 64 byte. the fifo size of two b channel are 128bytes. two extended external interrupt is designed for peripheral interrupt saving extra interrupt circuit design. one layer activation indication output can be programmed by microprocessor control or w6691 chip internal control. the dpll circuit is design in chip to generate the dcl and fsc signal for nt2 application. it can eliminate extra dpll circuit on board. in order to save a lot of crystal on board, w6691 can provide 7.68mhz osc signal for other chip needs the clock in te or nt2 application. preliminary w6691 publication release date: sep 2001 9 revision 1.1 2. features ? full duplex 2b+d s/t interface transceiver compliant with itu i.430 recommendation ? one d channel hdlc controller - maskable address recognition - transparent (hdlc) mode - fifo buffer (2 * 64) ? two b channel hdlc controller - maskable address recognition - transparent (hdlc) mode - fifo buffer (2 * 128) ? various b channel switching capabilities and pcm intercom ? two pcm codec interfaces for speech and pots application ? gci interface connects with other peripheral device in te, lt-s and lt-t mode. ? multi-frame synchronization ? 8-bits intel mode or motorola mode interface accesses b channel and command/indication channel. ? the timing clock recovery depends on operating mode. ? dpll circuit designed in chip for nt2 application. ? four kind of the extended interrupt trigger mode. ? two kind of output interrupt polarity selection can be programmed.(positive level and negative level) ? added reset signal to reset other chip. ? loop back function for testing. ? layer1 activate indication output can be connected to led ? two of programmable timer ? 3.3 volt power supply ? 3.3 volt output; maximum input is 5.0volt ? advanced cmos technology ? 64 pin lqfp or 68 pin plcc package preliminary w6691 publication release date: sep 2001 10 revision 1.1 3. pin configurations d c l o f s c o v s s v d d c k l t t o u t 2 x t a l 2 x t a l 1 v s s a s r 1 v d d a s x 1 s x 2 c n c c p c vdd vss c16.384 mbs pfck2 pfck1 pbck ptxd prxd vdd vss du dd fsc dcl int# c p t e s p t r s t # m b i t v s s a c t l 1 s o s c 7 6 8 r d # a l e c s # vdd vss isdn s/t interface access controller w6691 12 34 5 6 7 8 9 10 11 12 13 14 15 16 18 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 wr# ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 v d d s r 2 m1 m0 fig.3.1 w6691 pin configuration - intel bus mode preliminary w6691 publication release date: sep 2001 11 revision 1.1 pin configurations, continued d c l o f s c o v s s v d d c k l t t o u t 2 x t a l 2 x t a l 1 v s s a s r 1 v d d a s x 1 s x 2 c n c c p c vdd vss c16.384 mbs pfck2 pfck1 pbck ptxd prxd vdd vss du dd fsc dcl int# c p t e s p t r s t # m b i t v s s a c t l 1 s o s c 7 6 8 r w a l e c s # a 7 vdd vss isdn s/t interface access controller w6691 12 34 5 6 7 8 9 10 11 12 13 14 15 16 18 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ds# a 6 d7 d6 d5 d4 d3 d2 d1 d0 v d d s r 2 m1 m0 a 5 a 4 a 3 a2 a1 a0 preliminary w6691 publication release date: sep 2001 12 revision 1.1 fig.3.2 w6691 pin configuration ? motorola bus mode preliminary w6691 publication release date: sep 2001 13 revision 1.1 4. pin description table 4.1 w6691 pin descriptions note : the suffix " # " indicates an active low signal. in intel or motorola bus mode, all unspecified pins must be left unconnected. pin name pin number type functions intel bus mode (enabled when mbs=high) mbs 52 i microprocessor bus selector (mbs). this pin must be pulled to high. ad7-0 23, 24, 25, 26, 27, 28, 29, 30 i/o multiplexed address and data bus. during the address phase, ad7-0 contains 8-bit physical address. during the data phase, ad7-ad0 contains data. cs# 11 i chip select. ale 10 i address latch enable. used to latch addresses. rd# 9 i read. wr# 22 i write. rst# 3 i reset. int# 64 o interrupt. the interrupt trigger level can be programmable by actl2:intol. it provides two types of interrupt trigger level including low level and high level. motorola bus mode (enabled when mbs=low) mbs 52 i microprocessor bus selector (mbs). this pin must be pulled to low. d7-d0 23, 24, 25, 26, 27, 28, 29, 30 i/o data bus. a7-a0 12, 13, 14, 15, 16, 17, 18, 19 i address bus. cs# 11 i chip select. ds# 20 i data strobe. rw 9 i read/write identify. high is for read and low is for write. rst# 3 i reset. int# 64 o interrupt. the interrupt trigger level can be programmable by actl2:intol. it provides two types of interrupt trigger level including low level and high level. preliminary w6691 publication release date: sep 2001 14 revision 1.1 gci bus dcl 63 i/o gci bus data clock : the frequency is twice data rate te mode : 1.536 mhz. lt-t/lt-s mode : 4.096 mhz. nt mode : 512khz it needs external pull-up. fsc 62 i/o gci bus frame synchronization clock: 8khz. it needs external pull-up. dd 61 i/o gci bus data downstream. it needs external pull-up. du 60 i/o gci bus data upstream. it needs external pull-up. cp/bcl 1 o cp ? output 512khz in lt-t mode. bcl ? output 768khz in te mode. fsco 34 o output fsco clock 8khz for lt-t/lt-s mode(nt2 application). it is synchronous to dclo. dclo 33 o output dpll clock 4.096mhz for lt-t/lt-s mode(nt2 application). it is synchronous to t interface clock. c16.384 51 i 16.384 mhz clock input for dpll circuit to generate fsco and dclo. pcm interface ( it is onl y used in te mode ) pfck1 54 o pcm port1 frame synchronization signal, with 8 khz repetition rate and 8 bits pulse width. pfck2 53 o pcm port2 frame synchronization signal, with 8 khz repetition rate and 8 bits pulse width. pbck 55 o pcm bit synchronization clock of 1.536 mhz. ptxd 56 o pcm transmit bus data output. a maximum of two channels with 64 kbits/s data rate can be multiplexed on this signal. it needs external pull-up. prxd 57 i pcm bus receive data input. a maximum of two channels with 64 kbits/s data rate can be multiplexed on this signal. it needs external pull-up. isdn si g nals and external cr y stal sr1 42 i s/t bus receiver input (negative). sr2 43 i s/t bus receiver input (positive). sx1 45 o s/t bus transmitter output (positive). preliminary w6691 publication release date: sep 2001 15 revision 1.1 sx2 46 o s/t bus transmitter output (negative). xtal1 40 i crystal or oscillator clock input. the clock frequency: 7.68mhz 100ppm. xtal2 41 o crystal clock output. left unconnected when using oscillator. functional test testp 2 i used to enable normal operation (1) or enter test mode (0). timer2 expiration output tout2 38 o timer 2 output. a square wave with 50 % duty cycle, 1~63 ms period can be generated. clock pulse osc768 8 o it provides output 7.68mhz clock. it does not synchronize to s interface. operating mode m0 31 i setting of operating mode m1 32 i setting of operating mode peripheral input port and output port actl1s 7 o activate layer1 status.this pin can be pulled to low level or programmed by microprocessor by actl2 : actl1s when layer1 operates in activate. actl2 : actl1s: 0: when layer 1 operates in activate state, actl1s pin is pulled to low level. in contrast, if layer 1 operates in deactivate state, actl1s pin is driven to high level. 1: the actl1 output level is programmed by microprocessor (actl2 : aclt1s). power and ground vdd 5, 22, 36, 49, 58 i digital power supply (3v 5%). vdda 44 i analog power supply (3v 5%). vss 6, 21, 35, 50, 59 i digital ground. vssa 41 i analog ground. preliminary w6691 publication release date: sep 2001 16 revision 1.1 5. system diagram and applications pcm codec x2 w6691 transfomer module pots circuit protection circuit microprocessor 4-wire s/t fax phone nt s interface fig.5.1 isdn ta with two pots connections preliminary w6691 publication release date: sep 2001 17 revision 1.1 te w6691 lt-s w6691 tsi lt-t w6691 clock generator t interface s interface 512khz 4.096mhz(dcl) 8khz(fsc) 7.68mhz 7.68mhz gci gci up fig.5.2 isdn paxb application preliminary w6691 publication release date: sep 2001 18 revision 1.1 6. block diagram the block diagram of w6691 is shown in figure 6.1 pcm codec b-channel switching line transceiver & ami/bin conversion gci circuit 4-wire s/t 2b+d 2b+d d hdlc controller fifo pcm port microprocessor interface circuit gci bus dpll1 and timing generator crystal/oscillator (7.68 mhz) i/o control pots circuit gci bus 2b+d slip buffer b1 hdlc controller fifo b2 hdlc controller fifo dpll2 fsco dclo c16.384 fig.6.1 w6691 functional block diagram preliminary w6691 publication release date: sep 2001 19 revision 1.1 7. functional descriptions 7.1.1 main block functions the functional block diagram of w6691 is shown in fig.6.1. the main function blocks are: - layer 1 function according to itu-t i.430 - b channel switching - gci bus interface - pcm port (x 2) and internal b channel switching - d channel hdlc controller - dpll 2 circiut generating 4.096 mhz clock for nt2 application the layer 1 function includes: - s/t bus transmitter/receiver - timing recovery using digital phase locked loop (dpll) circuit - layer 1 activation/deactivation - d channel access control - frame alignment - multi-frame synchronization - test functions the serial interface bus performs the multiplexing/demultiplexing of d and 2b channels. the b channel switching determines the connection between layer 1/gci, layer 2 and pcm. gci bus is for te, lt-s and lt-t mode applications. the pcm port provides two 64 kbps clear channels to connect to pcm codec chips. the d channel hdlc controller performs the lapd (link access procedure on the d channel) protocol according to itu-t i.441/q.921 recommendation. preliminary w6691 publication release date: sep 2001 20 revision 1.1 the peripheral simple i/o is used to control other peripheral devices such as codec, slic, dtmf detector, leds. 7.1.2 interface and operating modes the w6691 can be configured for the following application: isdn terminals --- te mode (m1=0 & m0=0) isdn subscriber line termination --- lt-s mode (m1=1 & m0=0) isdn trunk line termination ---lt-t mode (m1=0 & m0=1) te , lt-s and lt-t modes are configured by setting mode pins (m1 and m0). 7.2.1 s/t interface transmitter/receiver according to itu-t i.430, pseudo-ternary code with 100% pulse width is used in both directions of transmission on the s/t interface. the binary "1" is represented by no line signal (zero volt), whereas a binary "0" is represented by a positive or negative pulse. data transmissions on the s/t interface are arranged as frame structures. the frame is 250 s long and consists of 48 bits, which corresponds to a 192 kbit/s line rate. each frame carries two octets of b1 channel, two octets of b2 channel and four d channel bits. therefore, the 2b+d data rate is 144 kbit/s. the frame structure is shown in fig.7.1. the frame begin is marked by a framing bit, which is followed by a dc balancing bit. the first binary "0" following the framing bit balancing bit is of the same polarity as the framing bit balancing bit, and subsequent binary zeros must alternate in polarity. preliminary w6691 publication release date: sep 2001 21 revision 1.1 fig.7.1 frame structure at s/t interface there are three wiring configurations according to i.430 : point-to-point, short passive bus and extended passive bus. they are shown in fig.7.2. d l f l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 e d a f a n b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 e d m b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 e d s b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 e d 0 1 0 nt te d l f l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 l d l f a l b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 l d l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 l d l b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 l 0 1 0 te nt 48 bits in 250 s 2 bits offset f = framing bit l = dc balancing bit d = d channel bit e = d channel echo bit f a = auxiliary framing bit or q-bit n = bit set to a binary value n=f a b1 = bit within b channel 1 b2 = bit within b channel 2 a = bit used for activation s = bit used for s channel m = multiframe bit preliminary w6691 publication release date: sep 2001 22 revision 1.1 fig.7.2 w6691 wiring configuration in te applications the transmitter and receiver are implemented by differential circuits to increase signal to noise ratio (snr). the nominal differential line pulse amplitude at 100 ? termination is 750 mv, zero to peak. transformers with 1:1 turn ration are needed at transmitter and receiver for voltage level translation and dc isolation. to meet the electrical characteristic requirements in i.430, some additional circuits are needed. at the transmitter side, the external resistors (5 to 10 ? ) are used to adjust the output pulse amplitude and to meet the transmitter active impedance ( 20 ? ) when transmitting binary zeros. at the receiver side, the 1.8 k ? w6691 te tr tr nt 1 000 m (a) point-to-point configuration tr tr nt 100~200 m (b) short passive bus configuration w6691 te1 te8 . . . . . 10m tr tr nt 100~200 m (c) extended passive bus configuration w6691 te1 te8 . . . . . 10m 50m tr : terminating resistor preliminary w6691 publication release date: sep 2001 23 revision 1.1 resistors protect the device inputs, while the 10 k ? resistors (1.8 k ? +8.2 k ? ) limit the peak current in impedance tests. the diode bridge is used for overvoltage protection. fig.7.3 external transmitter circuitry sx1 sx2 5-10 ? 5-10 ? gnd vdd 2:1 100 ? preliminary w6691 publication release date: sep 2001 24 revision 1.1 fig.7.4 external receiver circuitry after hardware reset, the receiver may enter power down state in order to save power consumption. in this state, the internal clocks are turned off, but the analog level detector is still active to detect signal coming from the s interface. the power down state is left either by non-info 0 signal from s interface or c/i command from microprocessor. sr1 sr2 1.8k ? 1.8k ? gnd vdd 8.2k ? 8.2k ? 2:1 100 ? preliminary w6691 publication release date: sep 2001 25 revision 1.1 7.2.2 receiver clock recovery and timing generation 1) te mode a digital phase locked loop (dpll) circuit is used to derive the receiving clock from the received data stream in te mode application. this dpll uses a 7.68 mhz clock as reference. according to i.430, the transmit clock is normally delayed by 2 bit time from the receive clock. the "total phase deviation from input to output" is -7% to +15% of a bit period. in some cases, delay compensation may be needed to meet this requirement (see ops1-0 bits in d_ctl register). 2) lt-t mode in lt-t mode application, a digital phase locked loop (dpll) circuit is also used to derive the receiving clock(192khz) from the received data stream.w6691 generates a cp (clock pulse ) derived from the 192khz receiving clock with dpll. cp clock rate is 512khz or 1536khz. if cp clock is used to synchronize nt2 clock, w6691 provide a slip buffer to avoid slipping between dcl and cp. 3) lt-s mode in lt-s modes, a digital phase locked loop (dpll) circuit is used to derive the receiving clock from the received data stream. this dpll uses a 7.68 mhz clock as reference. table 7.1 output phase delay compensation table ops1 ops0 effect 0 0 no phase delay compensation 0 1 phase delay compensation 260 ns 1 0 phase delay compensation 520 ns 1 1 phase delay compensation 1040 ns w6691 does not need rc filter on receiver side, therefore zero delay compensation is selected normally. this is also the default setting. the pcm output clocks (pfck1-2, pbck) are locked to the s-interface timing with jitter. see the electrical specification. preliminary w6691 publication release date: sep 2001 26 revision 1.1 7.2.3 layer 1 activation/deactivation the layer 1 activation/deactivation procedures are implemented by a finite state machine according to te/lt-t/lt-s mode. the state transitions are triggered by signals received at s interface or commands issued from microprocessor. the state outputs signals to s interface and indication to microprocessor. the cix register is used by microprocessor to issue command, and the cir register is used by microprocessor to receive indication. some commands are used for special purposes. they are "layer 1 reset", "analog loopback", "send continuous zeros" and "send single zero". 7.2.3.1 states descriptions and command/indication codes in te/lt-t f3 deactivated without clock this is the "deactivated" state of itu-t i.430. the receive line awake unit is active except during a hardware reset pulse. after reset, once the indication "1111" has been read out, internal clocks will turn off and stay at this state if info 0 is received on the s line. the turn off time is approximate 93 ms. the eck command must be issued to activate the clocks. f3 deactivated with clock this state is identical to "f3 deactivated without clock" except the internal clocks are enabled. the state is entered by the eck command. the clocks are enabled approximately 0.5 ms to 4 ms after the eck command, depending on the crystal capacitances. (it is about 0.5 ms for 12pf to 33pf capacitance). f3 awaiting deactivation the w6691 enters this state after receiving info 0 (in states f5 to f8) for 16ms (64 frames). this time constant prevents spurious effect on s interface. any non-info 0 signal on the s interface causes transition to "f5 identifying input" state. if this transition does not occur in a specific time (500 - 1000 ms), the microprocessor may issue drc or eck command to deactivate layer 1. f4 awaiting signal this state is reached when an activate request command has been received. in this state, the layer 1 transmits info1 and info 0 is received from the s interface. the software starts timer t3 of i.430 when issuing activate request command. the software deactivates layer 1 if no signal other than info 0 has been received on s interface before expiration of t3. preliminary w6691 publication release date: sep 2001 27 revision 1.1 f5 identifying input after the receipt of any non-info 0 signal from nt, the w6691 ceases to transmit info 1 and awaits identification of info 2 or info 4. this state is reached at most 50 s after a signal different from info 0 is present at the receiver of the s interface. f6 synchronized when w6691 receives an activation signal (info 2), it responds with info 3 and waits for normal frames (info 4). this state is reached at most 6 ms after an info 2 arrives at the s interface (in case the clocks were disabled in "f3 deactivated without clock"). f7 activated this is the normal active state with the layer 1 protocol activated in both directions. from state "f6 synchronized" , state f7 is reached at most 0.5 ms after reception of info 4. from state "f3 deactivated without clock" with the clocks disabled, state f7 is reached at most 6 ms after the w6691 is directly activated by info 4. f8 lost framing this is the state where the w6691 has lost frame synchronization and is awaiting resynchronization by info 2 or info 4 or deactivation by info 0. special states: analog loop initiated on enable analog loop command, info 3 is sent by the line transmitter internally to the line receiver (info 0 is sent to the line). the receiver is not yet synchronized. analog loop activated the receiver is synchronized on info 3 which is looped back internally from the transmitter. the indication 'ti" or "ati" is sent depending on whether or not a signal different from info 0 is detected on the s interface. send continuous pulses a 96 khz continuous pulse with alternating polarities is sent. preliminary w6691 publication release date: sep 2001 28 revision 1.1 send single pulses a 2 khz , isolated pulse with alternating polarities is sent. layer 1 reset a layer 1 reset command forces the transmission of info 0 and disables the s line awake detector. thus activation from nt is not possible. there is no indication in reset state. the reset state can be left only with eck command. table 7.2 layer 1 command codes command symbol code description enable clock eck 0000 enable internal clocks layer 1 reset rst 0001 layer 1 reset send continuous pulses scp 0100 send continuous pulses at 96 khz send single pulses ssp 0010 send isolated pulses at 2 khz activate request at priority 8 ar8 1000 activate layer 1 and set d channel priority level to 8 activate request at priority 10 ar10 1001 activate layer 1 and set d channel priority to 10 enable analog loopback eal 1010 enable analog loopback deactivate layer 1 drc 1111 deactivate layer 1 and disable internal clocks table 7.3 layer 1 indication codes indication symbol code descriptions clock enabled ce 0111 internal clocks are enabled deactivate request downstream drd 0000 deactivation request by s interface, i.e info 0 received level detected ld 0100 signal received, receiver not synchronous activate request downstream ard 1000 info 2 received test indication ti 1010 analog loopback activated or continuous zeros or single zeros transmitted awake test indication ati 1011 level detected during test function a ctivate indication with priority class 1 ai8 1100 info 4 received, d channel priority is 8 or 9 preliminary w6691 publication release date: sep 2001 29 revision 1.1 a ctivate indication with priority class 2 ai10 1101 info 4 received, d channel priority is 10 or 11 clock disabled cd 1111 layer 1 deactivated, internal clocks are disabled 7.2.3.2 state transition diagrams in te/lt-t the followings are the state transition diagrams, which implement the activation/deactivation state matrix in i.430 (table 5/i.430). the "command" and "s receive" entries in each state octagon keep the state, the "indication" and "s transmit" entries in each state octagon are the state outputs. for example, at "f3 deactivated with clock" state, the layer 1 will stay at this state if the command is "eck" and the info 0 is received on s interface. at this state, it provides "ce" indication to the microprocessor and transmits info 0 on s interface. the "ar8/10" command causes transition to f4 and non-info 0 signal causes transition to f5. note that the command code writtern by the microprocessor in cix register and indication code written by layer 1 in cir register are transmitted repeatedly until a new code is written. preliminary w6691 publication release date: sep 2001 30 revision 1.1 note : 1. "^rst" means "not layer 1 reset command". 2. "any" means any signal other than i0, which has not yet been determined. 3. "^i0" means any signal other than i0 fig.7.5 layer 1 activation/deactivation state diagram - normal mode fig.7.5 layer 1 activation/deaction state diagram ? te/lt-t normal mode state com ind s receive s trans. f4 await. signal ar8/10 ce i0 i1 f5 ident. input ^rst 1) ld any 2) i0 f6 synchronized ^rst 1) ard i2 i3 f7 activated ar8/10 ai8/10 i4 i3 f8 lost framing ^rst 1) ld any 2) i0 f3 deact w/o clk drc cd i0 i0 f3 deact with clk eck ce i0 i0 f3 await. deact. ar8/10 drd i0 i0 notation: a r 8/ 1 0 a r 8/ 1 0 dr c e c k dr c dr c e c k e c k ^i 0 3) ^ i0 3) ^ i0 3) ^i 0 3) i0 i 0 i0 i0 i2 i4 i2 i4 lost framing i4 i2 lost framing preliminary w6691 publication release date: sep 2001 31 revision 1.1 fig.7.6 layer 1 activation/deactivation state diagram ? te/lt-t special mode state com ind s receive s trans. reset rst none ignored i0 send cont. pulses scp ti ignored ic 3) send sing. pulses ssp ti ignored is 4) ana. loop init. eal ce ignored i3 5) ana. loop act. eal ti/ati ignored i3 5) rst scp ssp eal eck y 2) y 2) y 2) y 2) i3 5) ^i3 5) notation: note : 1. rst can be issued at any state, while scp, scz and eal can be issued only at f3 or f7. 2. y is one of the commands : eck, drc, rst. 3. continuous pulses at 96 khz. 4. isolated pulses at 2 khz. 5. the info 3 is transmitted internally only. preliminary w6691 publication release date: sep 2001 32 revision 1.1 7.2.4 layer 1 activation /deactivation in lt-s mode 7.2.4.1 states descriptions and command/indication codes in lt-s mode g1 deactivated no any signal is detected on s interface and no any activation command is received in the c/i channel. g2 pending activation if info1 is detected on s interface or an ard command is received from layer2 ,the w6691 start to transmit info2. w6691 is waiting for receiving info3 from s interface. info2 is sent from w6691. g3 activated w6691 receives info3 ,then, it enters g3 activated state. the info4 is transmitted in this state. when the synchronization is lost, w6691 switch to transmit info2 instead of info4 and wait for receiving info3 to get synchronization again. g4 pending deactivation this state is requested by ddr (deactivate request). if info0 is received during 16ms or an internal timer2 expiration, the layer1 responses driu indication for layer2. g4 await deactivated the w6691 stays in this state and waits for driu report from layer2. if w6691 receives dra command from layer2, it enters g1 state. test mode continuous pulses continuous alternating 96 khz pulses are sent. test mode single pulses preliminary w6691 publication release date: sep 2001 33 revision 1.1 single alternating 2khz pulses are sent. table 7.4 layer 1 command codes command symbol code description deactivate down request ddr 0000 deactive layer1 and disable internal clocks send continuous pulses scp 0011 send continuous pulses at 96 khz send single pulses ssp 0010 send isolated pulses at 2 khz activate request downstream ard 1000 request layer1 activate info2/info4 sent deactivate request assure dra 1111 layer2 reponses deactivate acknowledgement to make sure layer1 can be deativate reset rst 0001 initialize to g4 or g1 state table 7.5 layer 1 indication codes indication symbol code descriptions signal synchronize ssyu 0100 received signal is not info3 and try to re-synchronize again activate request indication upstream ariu 1000 the info 1 signal detected is responsed to layer2. activate indication upstream aiu 1100 synchronous receiver deactivate request indication upstream driu 1111 1. timer2 expired 2. info 0 received during 25ms after deactivation request command reset indication rsti 0001 reset state indication test indication ti 0000 preliminary w6691 publication release date: sep 2001 34 revision 1.1 7.2.4.2 states transition diagram in lt-s mode fig.7.7 layer 1 activation/deactivation state diagram in lt-s is: continuous 96 khz pulse signal or single 2 khz pulse signal ard or i1 g1 deact ddr driu i0 i0 g2 pending act ddr/ard ariu i0/i1 i2 i3 g3 activated ddr/ard aiu ^i3 i4 ddr/ard ssyn i2 g4 pending deact ddr i0 i0/i1/i3 ddr aiu g4 await deact ddr driu i0 ddr ddr reset rest res i0 i0/i1/i3 test mode ti scp/ssp is i0/i1/i3 scp/ssp rst ddr i3 i3 lost of frame i0 during 25ms or t2 expire i0/i3 ard ard ard dra ddr ^i3 preliminary w6691 publication release date: sep 2001 35 revision 1.1 7.2.5 d channel access control the d channel access control includes collision detection and priority management. the collision detection is always enabled. the priority management procedure as specified in itu-t i.430 is fully implemented in w6691. a collision is detected if the transmitted d bit and the received echo bit do not match. when this occurs, d channel transmission is immediately stopped, and the echo channel is monitored to attempt the next d channel access. there are two priority classes: class 1 and class 2. within each class, there are normal and lower priority levels. table 7.8 d priority classes normal level lower level priority class 1 8 9 priority class 2 10 11 the selection of priority class is via the ar8/ar10 command. the following table summarizes the commands/indications used for setting the priority classes: table 7.9 d priority commands/indications command symbol code remarks activate request, set priority 8 ar8 1000 activation command, set d channel priority to 8 activate request, set priority 10 ar10 1001 activation command, set d channel priority to 10 indication abbr. remarks activate indication with priority 8 ai8 1100 info 4 received, d channel priority is 8 or 9 activate indication with priority 10 ai10 1101 info 4 received, d channel priority is 10 or 11 preliminary w6691 publication release date: sep 2001 36 revision 1.1 7.2.6 frame alignment the following sections describe the behavior of w6691 in respect to the cts-2 conformance test procedures for frame alignment. please refer to etsi-tm3 appendix b1 for detailed descriptions. 7.2.6.1 fainfa_1fr this test checks if te does not lose frame alignment on receipt of one bad frame. the pattern for the bad frame is defined as ix_96 khz. this pattern consists of alternating pulses at 96 khz during the whole frame. device settings result w6691 none pass 7.2.6.2 fainfb_1fr this test checks if te does not lose frame alignment on receipt of one ix_i4noflag frame which has no framing and balancing bit. device settings result w6691 none pass 7.2.6.3 fainfd_1fr this test checks if te does not lose frame alignment on receipt of one ix-i4viol16 frame. the ix_i4viol16 frame remains at binary "1" until the first b2 bit which is bit position 16. the pulse sequences are: framing bit, balancing bit, b2 bit, m bit, s bit, balancing bit. the te should reflect the received f a bit (f a ="1") in the transmitted frame. device settings result w6691 none pass preliminary w6691 publication release date: sep 2001 37 revision 1.1 7.2.7.4 fainfa_kfr this is to test the number k of ix_96 khz frames necessary for loss of frame alignment. device settings result w6691 k =2 pass 7.2.6.5 fainfb_kfr this is to test the number k of ix_i4noflag frames necessary for loss of frame alignment. device settings result w6691 k =2 pass 7.2.6.6 fainfd_kfr this is to test the number k of ix_i4noflag frames necessary for loss of frame alignment. device settings result w6691 k = 2 pass 7.2.6.7 faregain this is to test the number m of good frames necessary for regain of frame alignment. the te regains frame alignment at m+1 frame. the w6691 achieves synchronization after 5 frames, i.e m=4. device settings result w6691 m = 4 pass preliminary w6691 publication release date: sep 2001 38 revision 1.1 7.2.7multiframe synchronization as specified by itu-t i.430, the q bit is transmitted from te to nt in the position normally occupied by the auxiliary framing bit (f a ) in one frame out of 5, whereas the s bit is transmitted from nt to te. the s and q bit positions and multiframe structure are shown in table 7.10. the functions provided by w6691 are: - multiframe synchronization: synchronization is achived when the m bit pattern has been correctly received during 20 consecutive frames starting from frame number 1. note: criterion for multiframe synchronization is not defined in i.430 recommendation. - s bits receive and detect: when synchronization is achieved, the four received s bits in frames 1,6,11,16 are stored as s1 to s4 in the sqr register respectively. a change in the recived four bits (s1-4) is indicated by an interrupt. - multiframe synchronization monitoring: multiframe synchronization is constantly monitored. the synchronization state is indicated by the msyn bit in the sqr register. - q bits transmit and f a mirroring: when multiframe synchronization is achived, the four bits q1-4 stored in the sqxr register are transmitted as the four q bits (f a -bit position) in frames 1,6,11 and 16. otherwise the f a bit transmitted is a mirror of the received f a -bit. at loss of synchronization, the mirroring is resumed at the next f a -bit. - the multiframe synchronization can be disabled by setting mfd bit in the d_mode register. - a ccording to i.430 recommendation, the s/q channel can be used as operation and maintenance signalling channel. at transmitter, a s/q code for a message shall be repeated at least six times or as many as necessary to obtain the desired response. at receiver, a message shall be considered received only when the proper codes is received three consecutive times. preliminary w6691 publication release date: sep 2001 39 revision 1.1 table 7.10 multiframe structure in s/t interface frame number nt-to-te f a -bit position nt-to-te m bit nt-to-te s bit te-to-nt f a -bit position 1 2 3 4 5 one zero zero zero zero one zero zero zero zero s1 zero zero zero zero q1 zero zero zero zero 6 7 8 9 10 one zero zero zero zero zero zero zero zero zero s2 zero zero zero zero q2 zero zero zero zero 11 12 13 14 15 one zero zero zero zero zero zero zero zero zero s3 zero zero zero zero q3 zero zero zero zero 16 17 18 19 20 one zero zero zero zero zero zero zero zero zero s4 zero zero zero zero q4 zero zero zero zero 1 2 etc. one zero one zero s1 zero q1 zero preliminary w6691 publication release date: sep 2001 40 revision 1.1 7.2.8test functions the w6691 provides loop and test functions as follows: - digital loop via dlp bit in d_mode register: in the layer 2 block, the transmitted 2b+d data are internally looped (from hdlc transmitter to hdlc receiver), and in the pcm ports, the transmitted b channels are internally looped (from pcm inputs to pcm outputs). the clock timings are generated internally and are independent of the s bus timing. this loop function is used for test of pcm and higher layer functions, excluding layer 1. after hardware reset, w6691 will power down if s bus is not connected or if there is no signal on the s bus. in this case, the c/i command eck must be issued to power up the chip. - analog loop via the c/i command eal: the analog s interface transmitter is internally connected to the s interface receiver. when the receiver has synchronized itself to the internal info 3 signal, the message "test indication" or "awake test indication" is delivered to the cir register. no signal is transmitted over the s interface. in this mode, the s interface awake detector is enabled. therefore if a level (info 2/ info 4) is detected on the s interface, this will be reported by the "awake test indication (ati)" indication. - remote loopback via rlp bit in d_mode register: the digital 2b data received from the s interface receiver is loopbacked to the s interface transmitter. the d channel is not looped. when rlp is enabled, layer 1 d channel is connected to hdlc port and dlp cannot be enabled. - transmission of special test signals via layer 1 command: * send single pulses (ssp): to send isolated single pulses of alternating polarity, with pulse width of one bit time, 250 us apart, with a repetition frequency of 2 khz. * send continuous pulses (scp): to send continuous pulses of alternating polarity, with pulse width of bit time. the repetition frequency is 96 khz. preliminary w6691 publication release date: sep 2001 41 revision 1.1 fig.7.9 ssp and scp test signals 7.3 b channel switching w6691 provides five kinds of b channel switching function. 1. pcm and gci bus switch (sfctl : pgswh) : it determines the codec interface is to be operated in b channel. 1: pcm bus is selected to operate with codec. 0: gci bus is selected to operate with codec. 2. pcm remote loop back (sfctl : pcrlp) setting this bit activates the pcm channel remote loopback function. the transmitted pcm data to pcm channel are looped to received pcm channel. 3. pxc pcm cross-connect (scft : pxc) this bit determines whether or not the pcm ports are cross-connected with the b channel ports. the setting of pxc is independent of the bsw1-0 bits. 250 us (a) single pulses (b) continuous pulses preliminary w6691 publication release date: sep 2001 42 revision 1.1 pxc connection 0 pcm1 ? b1, pcm2 ? b2 1 pcm1 ? b2, pcm2 ? b1 4. b2sw1 / b2sw0 b2 channel switch these two bits determine b2 channel switch among pcm port , layer1/gci and layer2. 00: select b2 channel switch between layer2 and layer1/gci. 01: select b2 channel switch between layer1/gci and pcm. 10: select b2 channel switch between pcm and layer2. 5. b1sw1 / b1sw0 b1 channel switch these two bits determine b1 channel switch among pcm port , layer1/gci and layer2. 00: select b1 channel switch between layer2 and layer1/gci. 01: select b1 channel switch between layer1/gci and pcm. 10: select b1 channel switch between pcm and layer2. 7.4 pcm port there are two pcm ports in w6691. data is valid when respective pfck is high. the frame synchronization clocks (pfck1-2) are 8 khz and the bit synchronization clock (pbck) is 1.536 mhz. 7.5 d channel hdlc controller there are two hdlc protocols that are used for isdn layer 2 functions : lapd and lapb. their frame formats are shown below. preliminary w6691 publication release date: sep 2001 43 revision 1.1 lapb modulo 8 : flag (1 octet) address (1octet) control (1octet) information (0 or n octets) fcs (2 octets) flag (1 octet) control field bits 7 6 5 4 3 2 1 0 i frame n(r) p n(s) 0 s frame n(r) p/f s s 0 1 u frame m m m p/f m m 1 1 lapb modulo 128 : flag (1 octet) address (1octet) control (1 or 2 octets) information (0 or n octets) fcs (2 octets) flag (1 octet) 1st octet 2nd octet control field bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 i frame n(s) 0 n(r) p s frame x x x x s s 0 1 n(r) p/f u frame m m m p/f m m 1 1 lapd : modulo 128 only flag (1 octet) address (2 octets) control (2 octets) information (0 or n octets) fcs (2 octets) flag (1 octet) preliminary w6691 publication release date: sep 2001 44 revision 1.1 1st octet 2nd octet control field bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 i frame n(s) 0 n(r) p/f s frame 0 0 0 0 s s 0 1 n(r) p/f u frame m m m p/f m m 1 1 7.5.1 d channel message transfer modes the d channel hdlc controller operates in transparent mode. chracteristics: - receive frame address recognition - address comparison maskable bit-by-bit - flag generation / deletion - zero bit insertion/ deletion - frame check sequence (fcs) generation/ check with crc_itu-t note . the lapd protocol uses the crc_itu-t for frame check sequence. the polynominal is x 16 + x 12 + x 5 + 1. for address recognition, the w6691 provides four programmable registers for individual sapi and tei values, sap1-2 and tei1-2, plus two fixed values for group sapi and tei, sapg and teig. the sapg equals 02h(c/r=1) or 00h(c/r=0) which corresponds to sapi = 0. the teig equals ffh which corresponds to tei = 127. incoming frame with 1 st address octet= (sap1 or sap2 or sapg) and 2 nd address octet= (tei1 or tei2 or teig) will be stored in the receive fifo, with flag and fcs fields being discarded and stuffed bits being removed. preliminary w6691 publication release date: sep 2001 45 revision 1.1 the valid address combinations are : - sap1 and tei1 - sap1 and tei=127 - sap2 and tei2 - sap2 and tei=127 - sapi=0 and tei1 - sapi=0 and tei2 - sapi=0 and tei=127 the receive frame address comparisons can be disabled (masked) per bit basis by setting the d_sam and d_tam registers, but comparisons with the sapg or teig cannot be disabled. 7.5.2 reception of frames in d channel a 128-byte fifo is provided in the receive direction. the data movement is handled by interrupts. there are two interrupt sources: receive message ready (d_rmr) and receive message end (d_rme). the d_rmr interrupt indicates that at least 64 bytes of data have been received and the message/ frame is not ended. upon d_rmr interrupt, the microprocessor reads out 32 bytes of data from the fifo. the d_rme interrupt indicates the last segment of a message or a message with length 32 bytes has been received. the length of data is less than or equal to 32 and is specified in the d_rbcl register. if the length of the last segment of message is 32, only d_rme interrupt is generated and the rbc4-0 bits in d_rbcl register are 000000b. the data between the opening flag and the crc field are stored in d_rfifo. for lapd frame, this includes the address field, control field and information field. when a d_rmr or d_rme interrupt is generated, the micro-processor must read out the data from d_rfifo and issues the receive message acknowledgement command (d_cmdr: rack bit) to explicitly preliminary w6691 publication release date: sep 2001 46 revision 1.1 acknowledge the interrupt. the microprocessor must handle the interrupt before more than 32 bytes of data are received. this corresponds to a maximum microprocessor reaction time of 16 ms at 16 kbps data rate. if the microprocessor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt and status bit. 7.5.3 transmission of frames in d channel a 64-byte fifo is provided in the transmit direction. if the transmit fifo is ready (which is indicated by a d_xfr interrupt), the micro-processor can write up to 32 bytes of data into the fifo and use the xms command bit to start frame transmission. the hdlc transmitter sends the opening flag first and then sends the data in the transmit fifo. the microprocessor must write the address, control and information field of a frame into the transmit fifo. every time no more than 32 bytes of data are left in the transmit fifo, the transmitter generates a d_xfr interrupt to request another block of data. the microprocessor can then write further data to the transmit fifo and enables the subsequent transmission by issuing an xms command. if the data written to the fifo is the last segment of a frame, the microprocessor issues the xme (transmit message end) and xms command bits to finish the frame transmission. the transmitter then transmits the data in the fifo and appends crc and closing flag. if the microprocessor fails to respond the d_xfr interrupt within a given time (16 ms), a data underrun condition will occur. the w6691 will automatically reset the transmitter and send inter frame time fill pattern (all 1's) on d channel. the microprocessor is informed about this condition via an xdun (transmit data underrun) interrupt in d_exir register. the microprocessor must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. it is possible to abort a frame by issuing a d_cmdr:xrst (d channel transmitter reset) command. the xrst command resets the transmitter and causes a transmit fifo ready condition. after the microprocessor has issued the xme command, the successful termination of transmission is indicated by an d_xfr interrupt. preliminary w6691 publication release date: sep 2001 47 revision 1.1 the inter-frame time fill pattern must be all 1's, according to itu-t i.430. collisions which occur on the d channel of s interface will cause an d_exir:xcol interrupt. a xrst (transmitter reset) command must be issued and software must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. 7.6 gci mode serial interface bus the gci is a generalization and enhancement of the general purpose, serial interface bus. the channel structure of the gci mode is depicted below. the timing is compatible with siemens?s iom-2 mode. te mode timing te mode contains three channels. the structure of te mode is show in fig7.10. preliminary w6691 publication release date: sep 2001 48 revision 1.1 du / dd b1 b2 m0 d ci0 ci1 m1 ae e a ch0 ch1 ch2 fsc 125us b1 : 64 kbits/s b channel 1 b2 : 64 kbits/s b channel 2 m0 : monitor channel 0 d : 16kbits/s d channel ci0: 48kbits/s command / indication channel a/e : 16kbits monitor channel handshake signaling m1: monitor channel1 ci1: 48kbits/s command / indication channel fsc dcl fig.7.10 gci te mode channel structure non-te mode timing: non ?te mode timing is used lt-s and lt-t applications. the frame contains eight channel (ch0 ~ ch7) gci channels. all structure of the eight channels shown in fig7.11 is the same. preliminary w6691 publication release date: sep 2001 49 revision 1.1 fsc du / dd 125us b1 : 64 kbits/s b channel 1 b2 : 64 kbits/s b channel 2 m : monitor channel d : 16kbits/s d channel ci: 48kbits/s command / indication channel a/e : 16kbits monitor channel handshake signaling fsc dcl c0 c1 c2 c3 c4 c5 c6 c7 c0 c1 c2 b1 b2 m d ci ae c0 fig.7.11 gci non ?terminal mode channel structure 7.6.1 gci mode c/i channel handling 1) ci0 channel the command/indication channel 0 carries real-time status information between the w6691 and another device connected to the gci bus interface. preliminary w6691 publication release date: sep 2001 50 revision 1.1 one ci0 channel conveys the commands and indications between a layer 1 device and layer 2 device. this c/i0 channel is accessed via register cir (in receive direction, layer 1 to layer 2) and register cix (in transmit direction, layer 2 to layer 1). the c/i code is 4-bit long. ? in the receive direction, the code from layer 1 is continuously monitored, with an interrupt being generated anytime a change occurs. a new code must be found in two consecutive gci frames to be considered valid and to trigger a c/i code change interrupt status (double last look criterion). ? in the transmit direction, the code written in cix is continuously transmitted in the channel. 2) ci1 channel ci1 channel is responsible for real time communication between w6691 and other non-layer1 peripheral devices. it consists of six bits. this channel can be used only in te mode. c1x and c1r are used for ci1 channel access in both of transmitting and receiving direction. ci1 code changed is indicated by an interrupt without double last look criterion. this interrupt will set ci1 bit in gci_exir. 7.6.2 gci mode monitor channel handling the monitor channel protocol is a handshake protocol used for high speed information exchange between the w6691 and other devices. the monitor channel is necessary for: ? programming and controlling devices attached to the gci interface. ? data exchange between two microprocessor systems attached to two different devices on one gci backplane. use of the monitor channel avoids the necessity of a dedicated serial communication path between two systems. the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the monitor channel receiver (mor) and monitor channel transmit (mox) bits. when data is placed into the monitor channel and the ?a? bit is activated. this data will be transmitted repeatedly once per 8 khz frame until the transfer is acknowledged via the ?e? bit. the microprocessor may either enforce a 1 (idle state) in ?e?, ?a? bit by setting the control bit mrc or mxc (mocr register) to 0, or enable the control of these bits internally by the w6691 according to the monitor channel protocol. thus, before a data exchange can begin, the control bit mrc, or mxc should be set to 1 by the microprocessor. preliminary w6691 publication release date: sep 2001 51 revision 1.1 the relevant status bits are: ? for the reception of monitor data: mdr (monitor channel data received ) ? mer (monitor channel end of reception) ? for the transmission of monitor data: mda (monitor channel data acknowledged ) ? mab (monitor channel data abort) about the status bit mac( monitor channel transmit active) indicates whether a transmission is progress . ? if set mac = 0, the previous transmission has been terminated. before starting a transmission, the microprocessor should verify that the transmitter is inactive. ? if set mac = 1, after having written data into the monitor transmit channel (mox) register, the microprocessor sets this bit to 1. this enables the ?a? bit to go active (0), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. the receiving device stores the monitor byte in its mor (monitor receive channel) and generates a mdr (monitor channel data receive) interrupt status. alerted by the mdr interrupt, the microprocessor reads the mor register. when it is ready to accept data, it sets the ?e? control bit mrc to 1 to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it enables other monitor channel interrupts by setting monitor channel interrupt enable to 1. the first monitor channel byte is acknowledged by the receiving device setting the ?e? bit to 0. this causes a mda (monitor channel data acknowledge) interrupt status at the transmitter. a new monitor channel data byte can now be written by the microprocessor in mox register. the ?a? bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the ?a? bit active after sending it once in the inactive state. the receiver stores the monitor channel byte in mor register and generates a new mdr interrupt status. when the microprocessor has read the mor register , the receiver acknowledges the data by returning the ?e? bit active after sending it once in the inactive state. this in turn causes the transmitter to generate a mda interrupt status. this mda interrupt write data mdr interrupt read data mda interrupt handshake procedure is repeated as long as the transmitter has data to send. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor channel transmit control bit mxc to 0. this enforces an inactive (1) state in the ?a? bit. two frames of ?a? inactive signifies the end of a message. thus, a mer (monitor channel end of reception) interrupt status is generated by the receiver when the ?a? bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the ?e? bit control bit mrc to 0, which in turn enforces an inactive state in the ?e? bit. this marks the end of the transmission, making the mac (monitor channel active) bit return to 0. during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive ?e? bit value in two consecutive frames. this is effected by the microprocessor writing the ?e? bit control bit mrc to 0. an aborted transmission is indicated by a mab (monitor channel data abort) interrupt preliminary w6691 publication release date: sep 2001 52 revision 1.1 7.7 8-bit microprocessor interface at power up, the reset pin rst# must be asserted to initialize the chip. at rising edge of rst#, data value at mbs pin determines the operation modes: high for intel bus mode, low for motorola bus mode. preliminary w6691 publication release date: sep 2001 53 revision 1.1 8. register desrcriptions 8.1 d channel hdlc controller register address map table 8.1 d channel hdlc controller register address map offset access register name description 00 r d_rfifo d channel receive fifo 01 w d_xfifo d channel transmit fifo 02 w d_cmdr d channel command register 03 r/w d_mode d channel mode control 04 r_clear ista interrupt status register 05 r/w imask interrupt mask register 06 r_clear d_exir d channel extended interrupt 07 r/w d_exim d channel extended interrupt mask 08 reserved 09 reserved 0a r d_xsta d channel transmit status 0b r d_rsta d channel receive status 0c reserved 0d reserved 0e r/w d_sam d channel address mask 1 0f r/w d_sap1 d channel individual sapi 1 10 r/w d_sap2 d channel individual sapi 2 11 r/w d_tam d channel address mask 2 12 r/w d_tei1 d channel individual tei 1 13 r/w d_tei2 d channel individual tei 2 14 reserved 15 reserved preliminary w6691 publication release date: sep 2001 54 revision 1.1 16 r d_rbch d channel receive frame byte count high 17 r d_rbcl d channel receive frame byte count low 8.2 gci bus control register address map table 8.2 gci bus control register address map offset access register name description 18 w csel gci bus cahnnel selection register 19 reserved 1a r/w cir command/indication receive 1b r/w cix command/indication transmit 1c r sqr s/q channel receive register 1d r/w sqx s/q channel transmit register 1e reserved 1f reserved 20 r/w mo0r monitor receive channel 0 21 r/w mo0x monitor transmit channel 0 22 r_clear mo0i monitor channel 0 interrupt 23 r/w mo0c monitor channel 0 control register 24 reserved 25 reserved 26 r/w gcr gci mode control/ status register 27 r mo1r monitor receive channel 1 28 r/w mo1x monitor transmit channel 1 29 r_clear mo1i monitor channel 1 interrupt 2a r/w mo1c monitor channel 1 control 2b reserved 2c reserved 2d reserved 2e reserved preliminary w6691 publication release date: sep 2001 55 revision 1.1 2f reserved 30 reserved 31 r ci1r gci ci1 indication 32 r/w ci1x gci ci1 command 33 reserved 34 r_clear gci_exir gci extended interrupt 35 r/w gci_exim gci extended interrupt mask 8.3 miscellaneous register address map table 8.3 miscellaneous register address map offset access register name description 36 reserved 37 reserved 38 r/w timr1 timer 1 39 r/w timr2 timer 2 3a r/w pcr peripheral control register 3b r/w piodr peripheral i/o data register 3c r/w sfctl switch function controll register 3d r/w actl1 auxiliary control register 1 3e r/w actl2 auxiliary control register 2 3f r/w actl3 auxiliary control register 3 8.4 d channel hdlc controller register memory map table 8.4 d channel hdlc controller register memory map offset r/w name 7 6 5 4 3 2 1 0 00 r d_rfifo preliminary w6691 publication release date: sep 2001 56 revision 1.1 offset r/w name 7 6 5 4 3 2 1 0 01 w d_xfifo 02 w d_cmdr rack rrst 0 stt1 xms 0 xme xrst 03 r/w d_mode 0 ract xact s_rlpd 0 mfd l2_dlp s_rlp 04 r_clr ista d_rmr d_rme d_xfr int1 int0 d_exi b1_exi b2_exi 05 r/w imask d_rmr d_rme d_xfr int1 int0 d_exi b1_exi b2_exi 06 r_clr d_exir rdov xdun xcol tin2 gci icc t1exp scc 07 r/w d_exim rdov xdun xcol tin2 gci icc t1exp scc 08 reserved 09 reserved 0a r d_xsta xdow 0 xbz 0 0 0 0 0 0b r d_rsta 0 rdov crce rmb 0 0 0 0 0c reserved 0d reserved 0e r/w d_sam sam7 sam6 sam5 sam4 sam3 sam2 sam1 sam0 0f r/w d_sap1 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 10 r/w d_sap2 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 11 r/w d_tam tam7 tam6 tam5 tam4 tam3 tam2 tam1 tam0 12 r/w d_tei1 ta17 ta16 ta15 ta14 ta13 ta12 ta11 ta10 13 r/w d_tei2 ta27 ta26 ta25 ta24 ta23 ta22 ta21 ta20 14 reserved 15 reserved 16 r d_rbch vn1 vn0 lov rbc12 rbc11 rbc10 rbc9 rbc8 17 r d_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 preliminary w6691 publication release date: sep 2001 57 revision 1.1 8.5 gci bus register memory map table 8.5 gci bus register memory map offset r/w name 7 6 5 4 3 2 1 0 18 r/w csel 0 0 0 0 0 csel2 csel1 csel0 19 reserved 1a r cir 0 0 0 bas cord3 cord2 cord1 cord0 1b r/w cix 0 0 0 bac cord3 cord2 cord1 cord0 1c r sqr 0 0 msyn 0 s1 s2 s3 s4 1d r/w sqx 0 0 0 0 q1 q1 q1 q1 1e reserved 1f reserved 20 r mo0r 21 r/w mo0x 22 r_clr mo0i 0 0 0 0 mdr0 mer0 mda0 mab0 23 r/w mo0c 0 0 0 0 mrie0 mrc0 mxie0 mxc0 24 reserved 25 reserved 26 r gcr mac0 mac1 0 0 0 0 0 0 27 r mo1r 28 r/w mo1x 29 r_clr mo1i 0 0 0 0 mdr1 mer1 mda1 mab1 2a r/w mo1c 0 0 0 0 mrie1 mrc1 mxie1 mxc1 2b reserved 2c reserved 2d reserved 2e reserved 2f reserved 30 reserved 31 r ci1r 0 0 ci1r_6 ci1r_5 ci1r_4 ci1r_3 ci1r_2 ci1r_1 preliminary w6691 publication release date: sep 2001 58 revision 1.1 offset r/w name 7 6 5 4 3 2 1 0 32 r/w ci1x 0 0 ci1x_6 ci1x_5 ci1x_4 ci1x_3 ci1x_2 ci1x_1 33 reserved 34 r_clr gci_exir 0 0 0 mo1c mo0c 0 0 ci1 35 r/w gci_exim 1 1 1 mo1c 0 0 0 ci1 8.6 miscellaneous register memory map table 8.6 miscellaneous register memory map offset r/w name 7 6 5 4 3 2 1 0 36 reserved 37 reserved 38 r/w timr1 t1md cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 39 r/w timr2 tmd tidle tcn5 tcn4 tcn3 tcn2 tcn1 tcn0 3a r/w pcr 0 0 0 0 oe3 oe2 oe1 oe0 3b r/w piodr 0 0 0 0 io3 io2 io1 io0 3c r/w sfctl 0 pgswh pcrlp pxc b2sw1 b2sw0 b1sw1 b1sw0 3d r/w actl1 0 0 srst 0 0 pd ops1 ops0 3e r/w actl2 0 actl1 lc 0 spu 0 0 0 3f r/w actl3 0 intol 0 0 0 0 0 0 8.7 d channel hdlc controller register description 8.7.1 d_ch receive fifo d_rfifo read address 00h the d_rfifo has a length of 64 bytes. after a d_rmr interrupt, exactly 32 bytes are available. after a d_rme interrupt, the number of bytes available equals rbc4-0 bits in the d_rbcl register. preliminary w6691 publication release date: sep 2001 59 revision 1.1 8.7.2 d_ch transmit fifo d_xfifo write address 01h the d_xfifo has a length of 64 bytes. after an d_xfr interrupt, up to 32 bytes of data can be written into this fifo for transmission. at the first time transmission, up to 64 bytes of data can be written. 8.7.3 d_ch command register d_cmdr write address 02h value after reset: 00h 7 6 5 4 3 2 1 0 rack rrst 0 stt1 xms 0 xme xrst rack receive acknowledge after a d_rmr or d_rme interrupt, the processor must read out the data in d_rfifo and then sets this bit to acknowledge the interrupt. writing ?0? to this bit has no effect. if rack bit is set to ?1? for operating ?receiver acknowledge?, it is not necessary to reset rack bit to ?0? by host processor. that is to say, once rack is set to ?1?, rack bit is reset to ?0? by w6691 automatically. rrst receiver reset setting this bit resets the d_ch hdlc receiver and clears the d_rfifo data. writing ?0? to this bit has no effect. if rrst bit is set to ?1? for operating ?receiver reset?, it is not necessary to reset rrst bit to ?0? by host processor. that is to say, once rrst is set to ?1?, rrst bit is reset to ?0? by w6691 automatically. stt1 start timer 1 the timer 1 is started when this bit is set to one. the timer is stopped when it expires or by a write of the timr1 register. writing ?0? to this bit has no effect. if sst1 bit is set to ?1? for operating ?start timer1?, it is not necessary to reset stt1 bit to ?0? by host processor. that is to say, once stt1 is set to ?1?, stt1 bit is reset to ?0? by w6691 automatically. preliminary w6691 publication release date: sep 2001 60 revision 1.1 xms transmit message start/continue setting this bit will start or continue the transmission of a frame. the opening flag is automatically added by the hdlc controller. writing ?0? to this bit has no effect. if xms bit is set to ?1? for operating ?transmit message start/continue?, it is not necessary to reset xms bit to ?0? by host processor. that is to say, once xms is set to ?1?, xms bit is reset to ?0? by w6691 automatically. xme transmit message end setting this bit indicates the end of frame transmission. the d_ch hdlc controller automatically appends the crc and the closing flag after the data transmission. writing ?0? to this bit has no effect. if xme bit is set to ?1? for operating ?transmit message end?, it is not necessary to reset xme bit to ?0? by host processor. that is to say, once xme is set to ?1?, xme bit is reset to ?0? by w6691 automatically. note : if the frame 32 bytes, xme plus xms commands must be issued at the same time. xrst transmitter reset setting this bit resets the d_ch hdlc transmitter and clears the d_xfifo. the transmitter will send inter frame time fill pattern (which is 1's) immediately. this command also results in a transmit fifo ready condition. writing ?0? to this bit has no effect. if xrst bit is set to ?1? for operating ?transmit reset?, it is not necessary to reset xme bit to ?0? by host processor. that is to say, once xrst is set to ?1?, xrst bit is reset to ?0? by w6691 automatically. 8.7.4 d_ch mode register d_mode read/write address 03h value after reset : 00h 7 6 5 4 3 2 1 0 0 ract xact 0 s_rlpd mfd l2_dlp s_rlp ract receiver active setting this bit activates the d_ch hdlc receiver. this bit can be read. the receiver must be in active state in order to receive data. note: the receiver is deactive after hardware reset or software reset. preliminary w6691 publication release date: sep 2001 61 revision 1.1 xact transmitter active setting this bit activates the d_ch hdlc transmitter. this bit can be read. the transmitter must be in active state in order to transmit data. note: the transmitter is deactive after hardware reset or software reset. s_rlpd s interface remote loopback with d channel loopback setting this bit to "1" activates the remote loopback function. the received 2b channels from the s interface are looped to the transmitted 2b channels of s interface. the received d channel from the s interface is also looped to transmitted d channel of s interface in the loopback function. mfd multiframe disable this bit is used to enable or disable the multiframe structure on s/t interface : 0 : multiframe is enabled 1 : multiframe is disabled l2_dlp layer2 digital loopback setting this bit activates the layer2 digital loopback function. the transmitted digital 2b+d channels are looped to the received 2b+d channels. note that after hardware reset, the internal clocks will turn off if the s bus is not connected or if there is no signal on the s bus. in this case, the c/i command eck must be issued to enable loopback function. s_rlp s interface remote loopback setting this bit to "1" activates the remote loopback function. the received 2b channels from the s interface are looped to the transmitted 2b channels of s interface. the received d channel from the s interface is not looped to transmitted d channel of s interface in this loopback function. . 8.7.5 interrupt status register ista read_clear address 04h value after reset : 00h 7 6 5 4 3 2 1 0 d_rmr d_rme d_xfr int1 int0 d_exi b1_exi b2_exi preliminary w6691 publication release date: sep 2001 62 revision 1.1 d_rmr d_ch receive message ready a 64-byte data is available in the d_rfifo. the frame is not complete yet. d_rme d_ch receive message end the last part of a frame with length > 32 bytes or a whole frame with length 32 bytes has been received. the whole frame length is obtained from d_rbch + d_rbcl registers. the length of data in the d_rfifo equals: data length = rbc4-0 if rbc4-0 0 data length = 32 if rbc4-0 =0 d_xfr d_ch transmit fifo ready this bit indicates that the transmit fifo is ready to accept data. up to 32 bytes of data can be written into the d_xfifo. an d_xfr interrupt is generated in the following cases : - after an xms command, when 32 bytes of xfifo is empty - after an xms together with an xme command is issued, when the whole frame has been transmitted - after an xrst command - after hardware reset or software reset int1 int1 interrupt if the int1 bit is set to ?1?, this bit indicates that interrupt trigger occurs at int1 pin. int0 int0 interrupt if the int0 bit is set to ?1?, this bit indicates that interrupt trigger occurs at int0 pin. d_exi d_ch extended interrupt this bit indicates that at least one interrupt bit is set in d_exir register. note : a read of the ista register clears all bits except d_exi, d_exi bit is cleared when all bits in d_exir register are cleared. preliminary w6691 publication release date: sep 2001 63 revision 1.1 b1_exi b1_ch extended interrupt this bit indicates that at least one interrupt bit has been set in b1_exir register. b2_exi b2_ch extended interrupt this bit indicates that at least one interrupt bit has been set in b2_exir register. 8.7.6 interrupt mask register imask read/write address 05h value after reset: ffh 7 6 5 4 3 2 1 0 d_rmr d_rme d_xfr int1 int0 d_exi b1_exi b2_exi setting the bit to "1" masks the corresponding interrupt source in ista register. masked interrupt status bits are read as zero. they are internally stored and pending until the mask bits are zero. note: setting the d_exi bit to "1" masks the interrupts in d_exir register. 8.7.7 d_ch extended interrupt register d_exir read_clear address 06h value after reset: 00h 7 6 5 4 3 2 1 0 rdov xdun xcol tin2 gci icc t1exp scc rdov receive data overflow frame overflow (too many short frames) or data overflow occurs in the receive fifo. in data overflow, the incoming data will overwrite the data in the receive fifo. if rdov interrupt occurs, software has to reset the receiver and discard the data received. preliminary w6691 publication release date: sep 2001 64 revision 1.1 xdun transmit data underrun this interrupt indicates the d_xfifo has run out of data. in this case, the w6691 will automatically reset the transmitter and send the inter frame time fill pattern (all 1's) on d channel. the microprocessor must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. xcol transmit collision this bit indicates a collision on the s-bus has been detected. w6691 will automatically reset the transmitter and software must wait until transmit fifo ready (via xfr interrupt), then, re-write data, and issue xms command to re-transmit the data. tin2 timer 2 expiration this bit is set when timer 2 counts down to zero. gci gci interrupt this bit is set when at least one bit is set in gci_exir register. icc indication channel change a change in the layer 1 indication code is detected. the actual value can be read from cir registers. t1exp timer 1 expiration expiration occurs in the timer 1. scc s channel change a change in multi-frame s channel is detected. the actual value can be read from sqr registers. 8.7.8 d_ch extended interrupt mask register d_exim read/write address 07 h value after reset: ffh 7 6 5 4 3 2 1 0 rdov xdun xcol tin2 gci icc t1exp scc preliminary w6691 publication release date: sep 2001 65 revision 1.1 setting the bit to "1" masks the corresponding interrupt source in d_exir register. masked interrupt status bits are read as zero. they are internally stored and pending until the mask bits are zero. note: all the interrupts in d_exir will be masked if the imask:d_exi bit is set to "1". 8.7.9 d_ch transmitter status register d_xsta read address 0ah value after reset: 00h 7 6 5 4 3 2 1 0 xdow 0 xbz 0 0 0 0 0 xdow transmit data overwritten at least one byte of data has been overwritten in the d_xfifo. this bit is set by data overwritten condition and is cleared only by xrst command. xbz transmitter busy this bit indicates the d_hdlc transmitter is busy. the xbz bit is set to?1? from the transmission of opening flag to the transmission of closing flag. 8.7.10 d_ch receive status register d_rsta read address 0bh value after reset: 20h 7 6 5 4 3 2 1 0 0 rdov crce rmb 0 0 0 0 rdov receive data overflow a "1" indicates that the d_rfifo is overflow. the incoming data will overwrite data in the receive fifo. the data overflow condition will set both the status and interrupt bits. it is recommended that software must read the rdov bit after reading data from d_rfifo when rmr or rme interrupt occurs. the software must preliminary w6691 publication release date: sep 2001 66 revision 1.1 abort the data and issue a rrst command to reset the receiver if rdov = 1. the frame overflow condition will not set this bit. crce crc error this bit indicates the result of frame crc check: 0: crc correct 1: crc error rmb receive message aborted a "1" means that a sequence of seven 1's was received and the frame is aborted. software must issue rrst command to reset the receiver. note : normally d_rsta register should be read by the microprocessor after a d_rme interrupt. the contents of d_rsta are valid only after a d_rme interrupt and remain valid until the frame is acknowledged via a rack bit. 8.7.11 d_ch sapi address mask d_sam read/write address 0eh value after reset: 00h 7 6 5 4 3 2 1 0 sam7 sam6 sam5 sam4 sam3 sam2 sam1 sam0 this register masks(disables) the first byte address comparison of the incoming frame. if the mask bit is "1" the corresponding bit comparisons with d_sap1, d_sap2 are disabled. comparison with sapg is always performed. each hdlc frame has two address byte. the first byte is spai and second byte is tei. the d_ch hdlc controller will compare these two bytes with contents of d_sapi1, dsap2 and d_tei1, d_tei2. if the hdlc frame sapi matches d_sapi1 or d_sap2 and the hdlc frame tei matches d_tei1 or d_tei2, the hdlc frame is captured and stored in d_channel receiving fifo. if comparison operation is enabled ( this means that the more than one bit in d_sam is set to ?1?), except the frame with matching address is stored, others are discarded. . if comparison operation is disabled ( this means that the all bits in d_sam are set to ?0?), all frame with any address combination are captured and stored in receiving fifo. the mask operation can be programmed by each bit respectively. the hdlc frame with sapg and /or teig address are always captured and stored. preliminary w6691 publication release date: sep 2001 67 revision 1.1 note : for the lapd frame, the least significant two bits are the c/r bit and ea =0 bit. it is suggested that the comparison with c/r bit be masked. ea=0 for two octet address frame e.g lapd, ea=1 for one octet address frame. 8.7.12 d_ch sapi1 register d_sap1 read/write address 0fh value after reset: 00h 7 6 5 4 3 2 1 0 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 this register contains the first choice of the first byte address of received frame. for lapd frame, sa17 - sa12 is the sapi value, sa11 is c/r bit and sa10 is zero. 8.7.13 d_ch sapi2 register d_sap2 read/write address 10h value after reset: 00h 7 6 5 4 3 2 1 0 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 this register contains the second choice of the first byte address of received frame. for lapd frame, sa27 - sa22 is the sapi value, sa21 is c/r bit and sa20 is zero. 8.7.14 d_ch tei address mask d_tam read/write address 11h value after reset: 00h 7 6 5 4 3 2 1 0 tam7 tam6 tam5 tam4 tam3 tam2 tam1 tam0 preliminary w6691 publication release date: sep 2001 68 revision 1.1 this register masks (disables) the second byte address comparison of the incoming frame. if the mask bit is "1" the corresponding bit comparisons with d_tei1, d_tei2 are disabled. . the hdlc frame with sapg and /or teig address are always captured and stored. note : for the lapd frame, the least significant bit is the ea =1 bit. 8.7.15 d_ch tei1 register d_tei1 read/write address 12h value after reset: 00h 7 6 5 4 3 2 1 0 ta17 ta16 ta15 ta14 ta13 ta12 ta11 ta10 ta17 - ta10 this register contains the first choice of the second byte address of received frame. for lapd frame, ta17 - ta11 is the tei value, ta10 is ea = 1. 8.7.16 d_ch tei2 register d_tei2 read/write address 13h value after reset: 00h 7 6 5 4 3 2 1 0 ta27 ta26 ta25 ta24 ta23 ta22 ta21 ta20 ta27 - ta20 this register contains the second choice of the second byte address of received frame. for lapd frame, ta27 - ta21 is the tei value, ta20 is ea = 1. preliminary w6691 publication release date: sep 2001 69 revision 1.1 8.7.17 d_ch receive frame byte count high d_rbch read address 16h value after reset: 40h 7 6 5 4 3 2 1 0 vn1 vn0 lov rbc12 rbc11 rbc10 rbc9 rbc8 vn1-0 chip version number this is the chip version number. it is read as 01b. lov length overflow a "1" in this bit indicates 8192 bytes are received and the frame is not yet complete. this bit is valid only after a d_rme interrupt and remains valid until the frame is acknowledge via the rack command. rbc12-8 receive byte count these bits are five most significant bits of the total frame length. these bits are valid only after a d_rme interrupt and remain valid until the frame is acknowledge via the rack command. 8.7.18 d_ch receive frame byte count low d_rbcl read address 17h value after reset: 00h 7 6 5 4 3 2 1 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 rbc7-0 receive byte count these bits are eight least significant bits of the total frame length. bits rbc4-0 also indicate the length of the data currently available in d_rfifo. these bits are valid only after an d_rme interrupt and remain valid until the frame is acknowledged via the rack command. preliminary w6691 publication release date: sep 2001 70 revision 1.1 8.8 gci bus register description 8.8.1 channel selection register csel read/write address 18h value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 0 csel2 csel1 csel0 csel2, csel1 and csel0 define w6691 locating in gci channel number operated in lt-s/ lt-t mode. 8.8.2 command/indication receive register cir read address 1ah value after reset: 0fh 7 6 5 4 3 2 1 0 0 0 0 bas codr3 codr2 codr1 codr0 bas bus access status indicate the state of the tic ?bus: 1: w6691 itself occupies the d and c/i channel. 0: another device occupies the d channel and c/i channel. codr3-0 layer 1 indication code value of the received layer 1 indication code. note these bits have a buffer size of two. if te mode is selected, codr3-0 bits are ci0 bits in gci bus channel. preliminary w6691 publication release date: sep 2001 71 revision 1.1 8.8.3 command/indication transmit register cix read/write address 1bh value after reset: 0fh 7 6 5 4 3 2 1 0 0 0 0 bac codx3 codx2 codx1 codx0 bac bus access control it is available if tic bus function is active. if this bit is set to ?1?, w6691 will try to access the tic-bus to occupy the c/i channel even if no d channel frame has to be transmitted. it should be reset when the access has been completed to grant a similar access to the other devices transmitting in that gci channel. codx3-0 layer 1 command code value of the command code is transmitted to layer 1. if te mode is selected, codx3-0 bits are ci0 bit in gci bus channel. reading this register returns the previous written value. 8.8.4 s/q channel receive register sqr read address 1ch value after reset: xxh 7 6 5 4 3 2 1 0 0 0 msyn 0 s1 s2 s3 s4 msyn multiframe synchronization when this bit is "1", a multiframe synchronization is achived, i.e the s/t receiver has synchronized to the received f a and m bit patterns. s1-4 received s bits these are the s bits received in nt to te direction in frames 1, 6, 11 and 16. s1 is in frame 1, s2 is in frame 6 etc. these four bits are double buffered. preliminary w6691 publication release date: sep 2001 72 revision 1.1 8.8.5 s/q channel transmit register sqx read/write address 1dh value after reset: 0fh 7 6 5 4 3 2 1 0 0 0 0 0 q1 q2 q3 q4 q1-4 transmitted q bits these are the transmitted q channels in f a bit positions in frames 1, 6, 11 and 16. q1 is in frame 1 and q2 is in frame 6 etc. reading this register returns the previous written value. 8.8.6 monitor receive channel 0 mo0r read address 20h value after reset: ffh 7 6 5 4 3 2 1 0 contains the monitor channel data received in gci monitor channel 0 according to the monitor channel protocol. 8.8.7 monitor transmit channel 0 mo0x read/write address 21h value after reset: ffh 7 6 5 4 3 2 1 0 preliminary w6691 publication release date: sep 2001 73 revision 1.1 contains the monitor channel data transmitted in gci monitor channel 0 according to the monitor channel protocol. 8.8.8 monitor channel 0 interrupt register mo0i read_clear address 22h value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 mdr0 mer0 mda0 mab0 mdr0 monitor channel 0 data receive mer0 monitor channel 0 end of reception mda0 monitor channel 0 data acknowledged the remote end has acknowledged the monitor byte being transmitted. mab0 monitor channel 0 data abort 8.8.9 monitor channel 0 control register mo0c read/write address 23h value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 mre0 mrc0 mie0 mxc0 mre0 monitor channel 0 receive interrupt enable monitor channel interrupt status mdr0, mer0 generation is enabled (1) or masked (0). preliminary w6691 publication release date: sep 2001 74 revision 1.1 mrc0 ?e? bit control determines the value of the ?e? bit: 0: ?e? bit always ?1?. in addition, the mdr0 interrupt is blocked, except for the first byte of a packet (if mre0=1). 1: ?e? bit is internally controlled by the w6691 according to monitor channel protocol. in addition, the mdr0 interrupt is enabled for all received bytes according to the monitor channel protocol (if mre0=1). mie0 monitor channel 0 transmit interrupt enable monitor interrupt status mda0, mab0 generation is enabled (1) or masked (0). mxc0 ?a? bit control determines the value of the ?a? bit: 0: ?a? bit is always 1. 1: ?a? bit is internally controlled by w6691 according to monitor channel protocol. 8.8.10 gci mode control/status register gcr read address 26h value after reset: 00h 7 6 5 4 3 2 1 0 mac0 mac1 0 0 0 0 0 0 mac0 monitor transmit channel 0 active (read only) data transmission is in progress in gci mode monitor channel 0. 0: the previous transmission has been terminated. before starting a transmission, the microprocessor should verify that the transmitter is inactive. 1: after having written data into the monitor transmit channel 0 (mo0x) register, the microprocessor sets this bit to 1. this enables the ?a? bit to go active (0), indicating the presence of valid monitor channel data (contents of mox) in the corresponding frame. mac1 monitor transmit channel 1 active (read only) data transmission is in progress in gci mode monitor channel 1. preliminary w6691 publication release date: sep 2001 75 revision 1.1 0: the previous transmission has been terminated. before starting a transmission, the microprocessor should verify that the transmitter is inactive. 1: after having written data into the monitor transmit channel 1 (mo1x) register, the microprocessor sets this bit to 1. this enables the ?a? bit to go active (0), indicating the presence of valid monitor channel data (contents of mox) in the corresponding frame. 8.8.11 monitor receive channel 1 register mo1r read address 27h value after reset: ffh 7 6 5 4 3 2 1 0 contains the monitor channel data received in gci monitor channel 1 according to the monitor channel protocol. 8.8.12 monitor transmit channel 1 register mo1x read/write address 28h value after reset: ffh 7 6 5 4 3 2 1 0 contains the monitor channel data transmitted in gci monitor channel 1 according to the monitor channel protocol. preliminary w6691 publication release date: sep 2001 76 revision 1.1 8.8.13 monitor channel 1 interrupt register mo1i read_clear address 29h value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 mdr1 mer1 mda1 mab1 mdr1 monitor channel 1 data receive mer1 monitor channel 1 end of reception mda1 monitor channel 1 data acknowledged the remote end has acknowledged the monitor byte being transmitted. mab1 monitor channel 1 data abort 8.8.14 monitor channel 1 control register mo1c read/write address 2ah value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 mre1 mrc1 mie1 mxc1 mre1 monitor channel 1 receive interrupt enable monitor channel interrupt status mdr1, mer1 generation is enabled (1) or masked (0). mrc1 ?e? bit control determines the value of the ?e? bit: 0: ?e? bit is always 1. in addition, the mdr1 interrupt is blocked, except for the first byte of a packet (if mre1=1). preliminary w6691 publication release date: sep 2001 77 revision 1.1 1: ?e? bit is internally controlled by the w6691 according to monitor channel protocol. in addition, the mdr1 interrupt is enabled for all received bytes according to the monitor channel protocol (if mre1=1). mie1 monitor channel 1 transmit interrupt enable monitor interrupt status mda1, mab1 generation is enabled (1) or masked (0). mxc1 ?a? bit control determines the value of the ?a? bit: 0: ?a? bit isalways 1. 1: ?a? bit internally controlled by the w6691 according to monitor channel protocol. 8.8.14 gci ci1 indication register ci1r read address 31h value after reset : undefined 7 6 5 4 3 2 1 0 0 0 ci1r_6 ci1r_5 ci1r_4 ci1r_3 ci1r_2 ci1r_1 ci1r_6-1 input data of gci ci1 channel. ci1r is only used in te mode selected. example application is data of arcofi's peripheral control interface input pins. 8.8.16 gci ci1 command register ci1x read/write address 32h value after reset: 3fh 7 6 5 4 3 2 1 0 0 0 ci1x_6 ci1x_5 ci1x_4 ci1x_3 ci1x_2 ci1x_1 preliminary w6691 publication release date: sep 2001 78 revision 1.1 ci1x6_1 transmitted data of gci ci1 channel. ci1r is only used in te mode selected. a read to these bits returns the previously written value. example application is data of arcofi's peripheral control interface output pins. 8.8.17 gci extended interrupt register gci_exir read_clear address 34h value after reset : 00h 7 6 5 4 3 2 1 0 0 0 0 mo1c mo0c 0 0 ci1 mo1c monitor channel 1 status change a change in the monitor channel 1 interrupt register ( mo1i ) has occurred. a new monitor channel byte is stored in the mo1r register. mo0c monitor channel 0 status change a change in the monitor channel 0 interrupt register (mo0i) has occurred. a new monitor channel byte is stored in the mo0r register. ci1 ci1 synchronous transfer interrupt when enabled, an interrupt is generated when there is a change in the received cir1_6-1 code without double last look criterion. it is only used in te-mode. 8.8.18 gci extended interrupt mask register gci_exim read/write address 35h value after reset: f7h 7 6 5 4 3 2 1 0 1 1 1 mo1c 0 0 0 ci1 preliminary w6691 publication release date: sep 2001 79 revision 1.1 bit 7-5 are fixed at ?1? and bit 3 is fixed at '0". this means mo0c interrupt cannot be masked. the interrupt is disabled when the bit is set. 8.9 miscellaneous register 8.9.1 timer 1 register timr1 read/write address 38h value after reset : 00h 7 6 5 4 3 2 1 0 t1md cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 t1md timer1 mode 0 = single count down mode: the timer counts once and generates a t1exp interrupt when expires. 1 = periodical count down mode: the timer counts periodically and generates an t1exp interrupt at each expiration. cnt6-0 count value the expiration time is defined as: t1 = cnt[6:0] * 0.1 second after writing this register, stt1 bit in d_cmdr register must be set to start the timer. this register can be read only after the timer has been started. the read value indicates the timer's current count value. in case layer 1 is not activated, a c/i command "eck" must be issued in addition to the stt1 command to start the timer. note: the timer is stopped when it expires in single count down mode(t1md=0) or timr1 register is re- written in both mode. preliminary w6691 publication release date: sep 2001 80 revision 1.1 8.9.2 timer 2 timr2 read/ write address 39h value after reset: 00h 7 6 5 4 3 2 1 0 tmd tidle tcn5 tcn4 tcn3 tcn2 tcn1 tcn0 tmd timer 2 mode 0: single count down mode: the timer starts when it is written a non-zero count value and stops when it reaches zero. 1: periodical count down mode: the timer starts when it is written a non-zero count value and counts down cyclically (periodically) with the count value. in both cases, a maskable interrupt tin2 is generated every time the timer reaches zero. when timer starts, pin tout2 changes to high and toggles every half count time. therefore, the period of tout2 equals count value. in both cases, timer counts with the new value if it is written again before expiration. the timer is stopped when it expires in single count mode (tmd=0), or zero count value is written in tcn5-0 (tmd=0 or 1). tidle tout2 idle this bit defines value of tout2 pin when timer is off. that is to say, the tidle determine the tout2 pin level is high or low when timer2 is off. tcn5-0 timer 2 count value 0: timer is off. 1 - 63: timer count value in unit of ms. preliminary w6691 publication release date: sep 2001 81 revision 1.1 8.9.3 peripheral control register pcr read/write address 3ah value after reset: 00h 7 6 5 4 3 2 1 0 0 0 0 0 oe3 oe2 oe1 oe0 only for plcc 68 pins : oe3 direction control for io3 0 : pin io3's output driver is disabled and input driver is enabled 1 : pin io3's output driver is enabled. note: the aclt2: int1m bit should be set to ?0?, int1/io3 pin can be as io. otherwise, it is configured as interrupt input. oe2 direction control for io2 0 : pin io2's output driver is disabled and input driver is enabled 1 : pin io2's output driver is enabled. note: the aclt2: int0m bit should be set to ?0?, int0/io2 pin can be as io. otherwise, it is configured as interrupt input. oe1 direction control for io1 0 : pin io1's output driver is disabled and input driver is enabled 1 : pin io1's output driver is enabled. oe0 direction control for io0 0 : pin io0's output driver is disabled and input driver is enabled 1 : pin io0's output driver is enabled. preliminary w6691 publication release date: sep 2001 82 revision 1.1 8.9.4 peripheral i/o data register piodr read/write address 3bh value after reset: 00 7 6 5 4 3 2 1 0 0 0 0 0 io3 io2 io1 io0 only for plcc 68 pins : io3 read or write data of pin io3 on read operation, the present value of pin io3 is read. on write operation, the data is driven to pin io3 only if pctl:oe3=1. note: the aclt2: int1m bit should be set to ?0?, int1/io3 pin can be as io. otherwise, it is configured as interrupt input. io2 read or write data of pin io2 on read operation, the present value of pin io2 is read. on write operation, the data is driven to pin io2 only if pctl:oe2=1. note: the aclt2: int0m bit should be set to ?0?, int0/io2 pin can be as io. otherwise, it is configured as interrupt input. io1 read or write data of pin io1 on read operation, the present value of pin io1 is read. on write operation, the data is driven to pin io1 only if pctl:oe1=1. io0 read or write data of pin io0 on read operation, the present value of pin io0 is read. on write operation, the data is driven to pin io0 only if pctl:oe0=1. preliminary w6691 publication release date: sep 2001 83 revision 1.1 8.9.5 sfctl switch functional control register read/write address 3ch value after reset : 00h 7 6 5 4 3 2 1 0 0 pgswh pcrlp pxc b2sw1 b2sw0 b1sw1 b1sw0 pgswh pcm and gci bus switch determines the codec interface is to be operated in b channel. 1: pcm bus is selected to operate with codec. 0: gci bus is selected to operate with codec. pcrlp pcm remote loop back setting this bit activates the pcm channel remote loopback function. the transmitted pcm data to pcm channel are looped to received pcm channel. pxc pcm cross-connect this bit determines whether or not the pcm ports are cross-connected with the b channel ports. the setting of pxc is independent of the bsw1-0 bits. pxc connection 0 pcm1 ? b1, pcm2 ? b2 1 pcm1 ? b2, pcm2 ? b1 b2sw1 / b2sw0 b2 channel switch these two bits determine b2 channel switch among pcm port , gci and layer2. 00: select b2 channel switch between layer2 and layer1/gci. 01: select b2 channel switch between layer1/gci and pcm. 10: select b2 channel switch between pcm and layer2. preliminary w6691 publication release date: sep 2001 84 revision 1.1 b1sw1 / b1sw0 b1 channel switch these two bits determine b1 channel switch among pcm port , gci and layer2. 00: select b1 channel switch between layer2 and layer1/gci. 01: select b1 channel switch between layer1/gci and pcm. 10: select b1 channel switch between pcm and layer2. 8.9.6 actl1 auxiliary control register 1 read/write address 3dh value after reset : 00h 7 6 5 4 3 2 1 0 0 0 srst 0 0 pd ops1 ops0 srst software reset when this bit is set to "1" 1ms at least, a software reset signal is activated. the effect of the reset signal is same as the hardware reset. this bit is not auto-clear, the software must write "0" to this bit to exit from the reset mode. note : when srst = 1, the chip is in reset state. read or write to any of the registers is inhibited at this moment. pd power down after hardware reset or software rest, pd bit is set to ?0?. it means w6691system clock is powered up after reset. 0: power down disable. w6691 system clock is not allowed to be powered down. 1: power down enable. if s interface can not receive non info 0 signal from line, w6691 enter power down mode automatically. preliminary w6691 publication release date: sep 2001 85 revision 1.1 ops1-0 output phase delay compensation select1-0 these two bits select the output phase delay compensation. ops1 ops0 effect 0 0 no output phase delay compensation 0 1 output phase delay compensation 260ns 1 0 output phase delay compensation 520 ns 1 1 output phase delay compensation 1040 ns 8.9.7 actl2 auxiliary control register2 read/write address 3eh value after reset : 40h 7 6 5 4 3 2 1 0 0 actl1s lc 0 spu 0 0 0 aclt1s activate layer1 status 0: when layer 1 operates in activate state, actl1s pin is pulled to low level. in contrast, if layer 1 operates in deactivate state, actl1s pin is driven to high level. 1: the actl1 output level is programmed by microprocessor.(actl2 : aclt1s) lc led controlled if aclts1is set to ?1?, lc bit is programmable by microprocessor. 0: it shows actls1 pin is driven to high level. 1: it shows actls1 pin is driven to low level. spu: software power up if spu is set to ?1?, w6691 can awaked from power down mode. preliminary w6691 publication release date: sep 2001 86 revision 1.1 8.9.8 actl3 auxiliary control register 3 read/write address 3fh value after reset : 00h 7 6 5 4 3 2 1 0 0 intol 0 0 0 0 0 0 intol interrupt output level configuration 0: it shows int pin is low active (open drain). 1: it shows int pin is high active. 8.10 b1 channel hdlc controller register address map table 8.7 b1 channel hdlc controller register address map offset access register name description 50 r b1_rfifo b1 channel receive fifo 51 w b1_xfifo b1 channel transmit fifo 52 reserved 53 r/w b1_cmdr b1 channel command register 54 r/w b1_mode b1 channel mode control 55 reserved 56 r_clear b1_exir b1 channel extended interrupt 57 r/w b1_exim b1 channel extended interrupt mask 58 r b1_star b1 channel status register 59 r/w b1_adm1 b1 channel address mask 1 5a r/w b1_adm2 b1 channel address mask 2 5b r/w b1_adr1 b1 channel address 1 5c r/w b1_adr2 b1 channel address 2 5d r b1_rbcl b1 channel receive frame byte count low 5e r b1_rbch b1 channel receive frame byte count high 5f r/w b1_idle b1 channel transmit idle pattern preliminary w6691 publication release date: sep 2001 87 revision 1.1 8.11 b1 channel hdlc controller register memory map table 8.8 b1 channel hdlc controller register memory map offset r/w name 7 6 5 4 3 2 1 0 50 r b1_rfifo 51 w b1_xfifo 52 reserved 53 r/w b1_cmdr rack rrst 0 0 0 xms xme xrst 54 r/w b1_mode mms itf ract xact b1_128 sw56 fts1 fts0 55 reserved 56 r_clr b1_exir 0 rmr rme rdov 0 0 xfr xdun 57 r/w b1_exim 1 rmr rme rdov 1 1 xfr xdun 58 r b1_star 0 rdov crce rmb 0 xdow 0 xbz 59 r/w b1_adm1 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 5a r/w b1_adm2 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 5b r/w b1_adr1 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 5c r/w b1_adr2 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 5d r b1_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 5e r b1_rbch 0 0 lov rbc12 rbc11 rbc10 rbc9 rbc8 5f r/w b1_idle idle7 idle6 idle5 idle4 idle3 idle2 idle1 idle0 8.11.1 b1_ch receive fifo b1_rfifo read address 50h the b1_rfifo is a 128-byte depth fifo memory with programmable threshold. the threshold value determines when to generate an interrupt. when more than a threshold length of data has been received, a rmr interrupt is generated. after an rmr interrupt, 64 or 96 bytes can be read out, depending on the threshold setting. in transparent mode, when the end of frame has been received, a rme interrupt is generated. after an rme interrupt, the number of bytes available is less than or equal to the threshold value. 8.11.2 b1_ch transmit fifo b1_xfifo write address 51h the b1_xfifo is a 128-byte depth fifo with programmable threshold value. the threshold setting is the same as b1_rfifo. preliminary w6691 publication release date: sep 2001 88 revision 1.1 when the number of empty locations is equal to or greater than the threshold value, a xfr interrupt is generated. after a xfr interrupt, up to 64 or 96 bytes of data can be written into this fifo for transmission. 8.11.3 b1_ch command register b1_cmdr read/write address 53h value after reset: 00h 7 6 5 4 3 2 1 0 rack rrst 0 0 0 xms xme xrst rack receive message acknowledge after a rmr or rme interrupt, the microprocessor reads out the data in b1_rfifo, it then sets this bit to explicitly acknowledge the interrupt. this bit is write only. it's auto-clear. writing ?0? to this bit has no effect. if rack bit is set to ?1? for operating ?receiver acknowledge?, it is not necessary to reset rack bit to ?0? by host processor. that is to say, once rack is set to ?1?, rack bit is reset to ?0? by w6691 automatically. rrst receiver reset setting this bit resets the b1_ch hdlc receiver. this bit is write-only. it's auto-clear. writing ?0? to this bit has no effect. if rrst bit is set to ?1? for operating ?receiver reset?, it is not necessary to reset rrst bit to ?0? by host processor. that is to say, once rrst is set to ?1?, rrst bit is reset to ?0? by w6691 automatically. xms transmit message start/continue in transparent mode, setting this bit initiates the transparent transmission of b1_xfifo data. the opening flag is automatically added to the message by the b1_ch hdlc controller. zero bit insertion is performed on the data. this bit is also used in subsequent transmission of the frame. in extended transparent mode, settint this bit activates the transmission of b1_xfifo data. no flag, crc or zero bit insertion is added on the data. this bit is write-only. it's auto-clear. writing ?0? to this bit has no effect. if xms bit is set to ?1? for operating ?transmit message start/continue?, it is not necessary to reset xms bit to ?0? by host processor. that is to say, once xms is set to ?1?, xms bit is reset to ?0? by w6691 automatically. xme transmit message end in transparent mode, setting this bit indicates the end of the whole frame transmission. the b1_ch hdlc controller transmits the data in fifo and automatically appends the crc and the closing flag sequence in transparent mode. preliminary w6691 publication release date: sep 2001 89 revision 1.1 in extended transparent mode, setting this bit stops the b1_xfifo data transmission. this bit is write-only. it's auto-clear. xrst transmitter reset setting this bit resets the b1_ch hdlc transmitter and clears the b1_xfifo. the transmitter will send inter frame time fill pattern on b channel in transparent mode, or idle pattern in extended transparent mode. this command also results in a transmit fifo ready condition. this bit is write only. it's auto-clear. 8.11.4 b1_ch mode register b1_mode read/write address 54h value after reset: 00h 7 6 5 4 3 2 1 0 mms itf ract xact b1_128k sw56 fts1 fts0 mms message mode setting determines the message transfer modes of the b1_ch hdlc controller: 0: transparent mode. in received direction, address comparison is performed on each frame. the frames with matched address are stored in b1_rfifo. flag deletion, crc check and zero bit deletion are performed. in transmitted direction, the data is transmitted with flag insertion, zero bit insertion and crc generation. 1: extended transparent mode. in received direction, all data are received and stored in the b1_rfifo. in transmitted direction, all data in the b1_xfifo are transmitted without alteration. itf inter-frame time fill defines the inter-frame time fill pattern in transparent mode. 0 : mark. the binary value "1" is transmitted. 1 : flag. this is a sequence of "01111110". ract receiver active "1": transmitter is active, 64 khz clock is provided. "0": transmitter is inactive, clock is low to save power. this bit is read/write. read operation returns the previously written value. note: the receiver is deactive after hardware reset or software reset. preliminary w6691 publication release date: sep 2001 90 revision 1.1 xact transmitter active "0": transmitter is active, 64 khz clock is provided. "1": transmitter is inactive, clock is low to save power. this bit is read/write. read operation returns the previously written value. note: the transmitter is deactive after hardware reset or software reset. b1_128 128k mode "1": both b1 and b2 channels in layer 1 are combined into single layer 2 channel. the layer 2 b1 channel can operates in transparent mode or extended transparent mode and layer 2 b2 channel is not used. "0": both b1 and b2 channels in layer 1 are not combined. this bit is read/write. read operation returns the previously written value. sw56 switch 56 traffic 0: the data rate in b1 channel is 64 kbps. 1: the data rate in b1 channel is 56 kbps. the most significant bit in each octet is fixed at "1". note : in 56 kbps mode, only transparent mode can be used. fts1-0 fifo threshold select these two bits determine the b1 channel receive and transmit fifo's threshold setting. an interrupt is generated when the number of received data or the number of vacancies in xfifo reaches the threshold value. fts1 fts0 threshold (byte) 0 0 64 0 1 reserved 1 0 96 1 1 not allowed 8.11.5 b1_ch extended interrupt register b1_exir read_clear address 56h value after reset: 00h 7 6 5 4 3 2 1 0 0 rmr rme rdov 0 0 xfr xdun preliminary w6691 publication release date: sep 2001 91 revision 1.1 rmr receive message ready at least a threshold lenth of data has been stored in the b1_rfifo. rme receive message end used in transparent mode only. the last block of a frame has been received. the frame length can be found in b1_rbch + b1_rbcl registers. the number of data available in the b1_rfifo equals frame lenth modulus threshold. the result of crc check is indicated by b1_star:crce bit. when the number of last block of a frame equals the threshold, only rme interrupt is generated. rdov receive data overflow data overflow occurs in the receive fifo. the incoming data will overwrite the data in the receive fifo. xfr transmit fifo ready this interrupt indicates that up to a threshold length of data can be written into the b1_xfifo. xdun transmit data underrun this interrupt occurs when the b1_xfifo has run out of data. in this case, the w6691 will automatically reset the transmitter and send the inter frame time fill pattern on b channel. the software must wait until transmit fifo ready condition (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. 8.11.6 b1_ch extended interrupt mask register b1_exim read/write address 57h value after reset: ffh 7 6 5 4 3 2 1 0 1 rmr rme rdov 1 1 xfr xdun setting the bit to "1" masks the corresponding interrupt source in b1_exir register. masked interrupt status bits are read as zero when b1_exir register is read. they are internally stored and pending until the mask bits are zero. all the interrupts in b1_exir will be masked if the imask : b1_exi bit is set to "1". 8.11.7 b1_ch status register b1_star read address 58h value after reset: 20h 7 6 5 4 3 2 1 0 0 rdov crce rmb 0 xdow 0 xbz preliminary w6691 publication release date: sep 2001 92 revision 1.1 rdov receive data overflow a "1" indicates that the d_rfifo is overflow. the incoming data will overwrite data in the receive fifo. the overflow condition will set both the status and interrupt bits. it is recommended that software must read the rdov bit after reading data from receive fifo at rmr or rme interrupt. the software must abort the data and issue a rrst command to reset the receiver if rdov = 1. crce crc error used in transparent mode only. this bit indicates the result of frame crc check: 0 : crc correct 1 : crc incorrect rmb receive message aborted used in transparent mode only. a "1" means that a sequence of seven 1's was received and the frame is aborted by the b1_hdlc controller. software must issue rrst command to reset the receiver. note : bit crce is valid only after a rme interrupt and remains valid until the frame is acknowledged via rack command. rmb must be polled after a rmr/rme interrupt. xdow transmit data overwritten at least one byte of data has been overwritten in the b1_xfifo. this bit is cleared only by xrst command. xbz transmitter busy the b1_hdlc transmitter is busy when xbz is read as "1". this bit may be polled. the xbz bit is active when an xms command was issued and the message has not been completely transmitted. 8.11.8 b1_ch address mask register 1 b1_adm1 read/write address 59h value after reset: 00h 7 6 5 4 3 2 1 0 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 ma17-10 address mask bits used in transparent mode only. these bits mask the first byte address comparisons. if the mask bit is "1", the corresponding bit comparison with b1_adr1 is disabled. 0: unmask comparison 1: mask comparison preliminary w6691 publication release date: sep 2001 93 revision 1.1 8.11.9 b1_ch address mask register 2 b1_adm2 read/write address 5ah value after reset: 00h 7 6 5 4 3 2 1 0 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma27-20 address mask bits used in transparent mode only. these bits mask the second byte address comparisons. if the mask bit is "1", the corresponding bit comparison with b1_adr2 is disabled. 0: unmask comparison 1: mask comparison 8.11.10 b1_ch address register 1 b1_adr1 read/write address 5bh value after reset: 00h 7 6 5 4 3 2 1 0 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 ra17-10 address bits used in transparent mode only. these bits are used for the first byte address comparisons. 8.11.11 b1_ch address register 2 b1_adr2 read/write address 5ch value after reset: 00h 7 6 5 4 3 2 1 0 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 ra27-20 address bits used in transparent mode only. these bits are used for the second byte address comparisons. 8.11.12 b1_ch receive frame byte count low b1_rbcl read address 5dh value after reset: 00h 7 6 5 4 3 2 1 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 preliminary w6691 publication release date: sep 2001 94 revision 1.1 rbc7-0 receive byte count used in transparent mode only. eight least significant bits of the total number of bytes are in a received frame. these bits are valid only after a rme interrupt and remain valid until the frame is acknowledge via the rack bit. 8.11.13 b1_ch receive frame byte count high b1_rbch read address 5eh value after reset: 00h 7 6 5 4 3 2 1 0 0 0 lov rbc12 rbc11 rbc10 rbc9 rbc8 lov message length overflow used in transparent mode only. a "1" in this bit indicates a received message 8192 bytes. this bit is valid only after rme interrupt and is cleared by the rack command. rbc12-8 receive byte count used in transparent mode only. five most significant bits of the total number of bytes are in a received frame. these bits are valid only after a rme interrupt and remain valid until the frame is acknowledge via the rack bit. note : the frame length equals rbc12-0. this length is between 1 and 8191 . after a rme interrupt, the number of data available in b1_rfifo is frame length modulus threshold. remainder = rbc12-0 mod threshold no of available data = remainder if remainder 0 or no of available data = threshold if remainder = 0 the remainder equals rbc5-0 if threshold is 64. 8.11.14b1_ch transmit idle pattern b1_idle read/write address 5fh value after reset: ffh 7 6 5 4 3 2 1 0 idle7 idle6 idle5 idle4 idle3 idle2 idle1 idle0 idle7-0 this pattern is transmitted when the transmitter is active and transmit fifo is empty. valid in extended transparent mode only. preliminary w6691 publication release date: sep 2001 95 revision 1.1 8.12 b2 channel hdlc controller register address map table 8.9 b2 channel hdlc controller register address map offset access register name description 70 r b2_rfifo b2channel receive fifo 71 w b2_xfifo b2 channel transmit fifo 72 reserved 73 r/w b2_cmdr b2 channel command register 74 r/w b2_mode b2 channel mode control 75 reserved 76 r_clear b2_exir b2 channel extended interrupt 77 r/w b2_exim b2 channel extended interrupt mask 78 r b2_star b2 channel status register 79 r/w b2_adm1 b2 channel address mask 1 7a r/w b2_adm2 b2 channel address mask 2 7b r/w b2_adr1 b2 channel address 1 7c r/w b2_adr2 b2 channel address 2 7d r b2_rbcl b2 channel receive frame byte count low 7e r b2_rbch b2 channel receive frame byte count high 7f r/w b2_idle b2 channel transmit idle pattern 8.13 b2 channel hdlc controller register memory map table 8.10 b2 channel hdlc controller register memory map offset r/w name 7 6 5 4 3 2 1 0 70 r b2_rfifo 71 w b2_xfifo 72 reserved 73 r/w b2_cmdr rack rrst 0 0 0 xms xme xrst 74 r/w b2_mode mms itf ract xact 0 sw56 fts1 fts0 75 reserved 76 r_clr b2_exir 0 rmr rme rdov 0 0 xfr xdun preliminary w6691 publication release date: sep 2001 96 revision 1.1 77 r/w b2_exim 1 rmr rme rdov 1 1 xfr xdun 78 r b2_star 0 rdov crce rmb 0 xdow 0 xbz 79 r/w b2_adm1 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 7a r/w b2_adm2 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 7b r/w b2_adr1 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 7c r/w b2_adr2 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 7d r b2_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 7e r b2_rbch 0 0 lov rbc12 rbc11 rbc10 rbc9 rbc8 7f r/w b2_idle idle7 idle6 idle5 idle4 idle3 idle2 idle1 idle0 the b2 channel hdlc controller register's definitions and functions are the same as those of b1 channel hdlc. please refer to b1 channel section for a detailed description. preliminary w6691 publication release date: sep 2001 97 revision 1.1 9. electrical characteristics 9.1 absolute maximum rating parameter symbol limit values unit voltage on any pin with respect to ground v s -0.4 to v dd +0.4 v ambient temperature under bias t a 0 to 70 c maximum voltage on v dd v dd 6 v 9.2 power supply the power supply is 5 v 5 %. 9.3 dc characteristics t a =0 to 70 c; v dd =5 v 5 %, v ssa =0 v, v ssd =0 v parameter symbol min max unit test conditions remarks low input voltage v il -0.4 0.8 v high input voltage v ih 2.0 v dd +0.4 v low output voltage v ol 0.4 v i ol = 12 ma high output voltage v oh 2.4 v analog power supply current: power down i cc 1.5 ma v dda =5v, s/t layer 1 in state ?f3 deactivated without clock? analog power supply current: activated i cc 6.5 ma v dd =5v, s/t layer 1 in state ?f7 activated? input leakage current i li 10 a 0 v < v in < v dd to 0v all pins except sx1,2, sr1,2 output lk i lo 10 a 0 v < v out < v dd to 0v all pins except sx1 2 sr1 2 preliminary w6691 publication release date: sep 2001 98 revision 1.1 leakage current sx1,2, sr1,2 absolute value of output pulse amplitude (v sx2 -v sx1 ) v x 2.03 2.10 2.31 2.39 v v r l =50 ? 1) r l =400 ? 1) sx1,2 transmitter output current i x 7.5 13.4 ma r l =5.6 ? 1) sx1,2 transmitter output impedance r x 30 23 k ? ? inactive or during binary one during binary zero (r l =50 ? ) sx1,2 note : 1) due to the transformer, the load resistance seen by the circuit is four times r l . capacitances t a =25 c, v dd = 5 v 5 %, v ssa = 0v, v ssd =0v, fc=1 mhz, unmeasured pins grounded. parameter symbol min. max. unit remarks input capacitance c in 7 pf all pins except sr1,2 i/o pin capacitance c io 7 pf all pins except sr1,2 output capacitance against v ssa c out 10 pf sx1,2 input capacitance c in 7 pf sr1,2 load capacitance c l 50 pf xtal1,2 recommended oscillator circuits crystal specifications parameter symbo l values unit frequency f 7.680 mhz frequency calibration tolerance max. 100 ppm load capacitance c l max. 50 pf oscillator mode fundamental note : the load capacitance c l depends on the crystal specification. the typical values are 33 to 47 pf. preliminary w6691 publication release date: sep 2001 99 revision 1.1 external ocsillator input (xtal1) clock characteristics parameter min. max. duty cycle 1:2 2:1 9.4 preliminary switching characteristics 9.4.1 pcm interface timing note 1: these drawings are not to scale. 2: the frequency of pbck is 1536 khz which includes 24 channels of 64 kbps data. the pfck1 and pfck2 are located at channel 1 and channel 2, each with a 8 x pbck duration. pbck (1.536mhz) pfck1 pfck2 ptxd prxd 24 chs ch 1 ch 2 port1 port1 port2 port2 port1 port1 port2 port2 preliminary w6691 publication release date: sep 2001 100 revision 1.1 detailed pcm timing parameter parameter descriptions min. nominal max. remarks ta1 pbck pulse high 325 unit = ns ta2 pbck pulse low 195 325 455 ta3 frame clock asserted from pbck 20 ta4 ptxd data delay from pbck 20 ta5 frame clock deasserted from pbck 20 ta6 ptxd hold time from pbck 10 ta7 prxd setup time to pbck 20 ta8 prxd hold time from pbck 10 note : the pcm clocks are locked to the s/t receive clock. at every two or three pcm frame time (125 s), pbck and pfck1, pfck2 may be adjusted by one local oscillator cycle (130 ns) in order to synchronize with s/t clock. this shift is made on the low level time of pbck and the high level time is not affected. this introduces jitters on the pbck, pfck1 and pfck2 with jitter amplitude 260 ns (peak-to-peak) and jitter frequency about 2.67~4 khz. pbck pfck1 pfck2 ptxd prxd ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 preliminary w6691 publication release date: sep 2001 101 revision 1.1 9.4.2 8-bit microprocessor timing intel mode read cycle timing intel mode write cycle timing t1 a le t3 t11 t5 t10 a d<7:0> rd# cs# t8 t2 a <7:0> d<7:0> a <7:0> t4 t9 t6 t7 t1 a le t3 t13 t12 t10 a d<7:0> wr# cs# t14 t2 a <7:0> d<7:0> a <7:0> t4 t15 t6 t7 preliminary w6691 publication release date: sep 2001 102 revision 1.1 motorola mode read cycle timing motorola mode write cycle timing a <7:0> t21 cs# rw ds# t19 t16 t18 t24 t20 t23 d<7:0> t22 t17 a <7:0> t27 cs# rw ds# t19 t16 t18 t29 t26 t28 d<7:0> t25 t17 preliminary w6691 publication release date: sep 2001 103 revision 1.1 parameter parameter descriptions min. max. remarks t1 ale pulse width 50 t2 address setup time to ale 15 t3 address hold time from ale 10 t4 address setup time to rd#, wr# 0 t5 rd# pulse width 110 t6 cs# setup time to rd#, wr# 0 t7 cs# hold time from rd#, wr# 0 t8 data output delay from rd# 50 t9 data float from rd# 25 t10 ale guard time 15 t11 rd# recovery time 70 t12 wr# pulse width 60 t13 wr# recovery time 70 t14 data setup time to wr# 35 t15 data hold time from wr# 10 t16 address setup time to ds# 25 t17 address hold time from ds# 10 t18 cs# setup time to ds# 10 t19 cs# hold time from ds# 10 t20 ds# read pulse width 110 t21 ds# read recovery time 70 t22 rw setup time to ds# read 0 t23 data output delay from ds# 110 t24 data hold time from ds# 25 t25 rw setup time to ds# write 0 t26 ds# write pulse width 60 t27 ds# write recovery time 70 t28 write data setup time to ds# 35 t29 write data hold time from ds# 10 preliminary w6691 publication release date: sep 2001 104 revision 1.1 9.5 ac timing test conditions t a = 0 to 70 c, v dd = 5 v 5 % inputs are driven to 2.4 v for logical 1 and 0.4 v for logical 0. measurements are made at 2.0 v for logical 1 and 0.8 v for logical 0. the ac testing input/output waveforms are shown below : ?. ?0?. 10. ordering information part number package type production flow w6691cd 64-pin lqfp commercial, 0 c to +70 0 c w6691cp 68-pin plcc commercial, 0 c to +70 0 c test point 2.0 0.8 2.0 0.8 2.4 0.4 device under test c load = 150pf preliminary w6691 publication release date: sep 2001 105 revision 1.1 11. package dimensions 64l lqfp (10 x 10 x 1.4mm ) 0 7 0 1.00 0.75 0.60 12.00 0.45 0.039 0.030 0.024 0.472 0.018 0.50 0.20 0.27 1.45 1.60 10.00 1.40 0.09 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.393 0.055 0.020 0.004 0.007 0.053 0.002 symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.008 0.20 7 0.393 10.00 0.472 12.00 0.006 0.15 0.003 0.08 3.5 3.5 preliminary w6691 publication release date: sep 2001 106 revision 1.1 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. unit 9-15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change withou t notice. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. unit 9-15, 22f, millennium city, no. 378 kwun tong rd; kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change withou t notice. |
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